mitsubishi microcomputers m37271mf-xxxsp m37271ef-xxxsp, m37271efsp single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller 34 time from the falling of the horizontal synchronizing signal to occurrence of the start bit 4 5 set value of the start bit position register 5 reference clock period << fig. 28. structure of caption position register (6) reference voltage generating circuit and comparator the composite video signal clamped by the clamping circuit is input to the reference voltage generating circuit and the comparator. 1 reference voltage generating circuit this circuit generates a reference voltage (slice voltage) by using the amplitude of the clock run-in pulse in line specified by the data slice line specification circuit. connect a capacitor between the v hold pin and the v ss pin, and make the length of wiring as short as possible so that a leakage current may not be generated. 2 comparator the comparator compares the voltage of the composite video signal with the voltage (reference voltage) generated in the reference voltage generating circuit, and converts the composite video signal into a digital value. (7) start bit detecting circuit this circuit detects a start bit at line decided in the data slice line specification circuit. for start bit detection, it is possible to select one of the following two types by using bit 1 of the clock run-in register 2 (address 00e7 16 ). 1 after the lapse of the time corresponding to the set value of the start bit position register (address 00e1 16 ), the first rising of the composite video signal is detected as a start bit. the time is set in bits 0 to 6 of the start bit position register (address 00e1 16 ) (refer to figure 26). set a value fit for the following conditions. figure 29 shows the structure of the start bit position register. time from the falling of the horizontal synchronizing signal to the last rising of the clock run-in fig. 29. structure of start bit position register caption position register (cp : address 00e0 16 ) specification main data slice line 70 100 fix these bits to ?00 2 70 start bit generating time time from a falling of the horizontal synchronizing signal to occurrence of a start bit = 4 5 set value (?0 16 to ?f 16 ? 5 reference clock period start bit position register (sp : address 00e1 16 ) dsc1 bit 7 control bit 0 : generation of 16 pulses 1 : generation of 16 pulses and detection of clock run-in
mitsubishi microcomputers m37271mf-xxxsp m37271ef-xxxsp, m37271efsp single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller 35 2 after a falling of the clock run-in pulse set in bits 2 to 0 of clock run- in detect register 2 (address 00e9 16 ) is detected, a start bit is detected by sampling a comparator output. a sampling clock for sampling is obtained by dividing the reference clock generated in the timing signal generating circuit by 13. figure 31 shows the structure of clock run-in detect register 2. the contents of bits 2 to 0 of clock run-in detect register 2 and bit 1 of clock run-in register 2 are written at a falling of the horizontal synchronizing signal. for this reason, even if an instruction for setting is executed, the contents of the register cannot be rewritten until a falling of the horizontal synchronizing signal. fig. 30. structure of clock run-in register 2 (8) clock run-in determination circuit this circuit sets a window in the clock run-in portion in the composite video signal, and then determinates clock run-in by counting the number of pulses in this window. set the time from a falling of the horizontal synchronizing signal to a start of the window by bits 0 to 5 of the window register (address 00e2 16 ; refer to figure 32). the window ends according to the contents of the setting of the start bit position register (refer to figure 29). fig. 32. structure of window register 70 1 start bit detecting method selection bit 0 : method 1 1 : method 2 clock run-in register 2 (cr2 : address 00e7 16 ) fix this bit to ?? fix these bits to ?00111 2 00111 1 fig. 31. structure of clock run-in detect register 2 70 window start time time from a falling of the horizontal synchronizing signal to a start of the window = 4 5 set value (?0 16 ?to ?f 16 ? 5 reference clock period window register (wn : address 00e2 16 ) fix these bits to ? 00 70 clock run-in pulses for sampling b2 b1 b0 0 0 0 : not available 0 0 1 : 1st pulse 0 1 0 : 2nd pulse 0 1 1 : 3rd pulse 1 0 0 : 4th pulse 1 0 1 : 5th pulse 1 1 0 : 6th pulse 1 1 1 : 7th pulse clock run-in detect register 2 (crd2 : address 00e9 16 ) data clock generating time time from detection of a start bit to occurrence of a data clock = (13 + set value) 5 reference clock period
mitsubishi microcomputers m37271mf-xxxsp m37271ef-xxxsp, m37271efsp single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller 36 fig. 33. structure of clock run-in register 1 fig. 36. structure of clock run-in detect registers 1and 3 fig. 35. window setting fig. 34. structure of clock run-in register 3 for the main data slice line, the count value of pulses in the window is stored in clock run-in register 1 (address 00e6 16 ; refer to figure 33). for the sub-data slice line, the count value of pulses in the window is stored in clock run-in register 3 (address 0209 16 ; refer to figure 34). when this count value is 4 to 6, it is determined as a clock run-in. accordingly, set the count value so that the window may start after the first pulse of the clock run-in (refer to figure 35). the contents to be set in the window register are written at a falling of the horizontal synchronizing signal. for this reason, even if an instruction for setting is executed, the contents of the register cannot be rewritten until a falling of the horizontal synchronizing signal. for the main data slice line, reference clock is counted in the period from a falling of the clock pulse set in bits 0 to 2 of the clock run-in detect register 2 (address 00e9 16 ) to the next falling. the count value is stored in bits 3 to 7 of the clock run-in detect register 1 (address 00e8 16 ) (when the count value exceeds 1f 16 , 1f 16 is held). for the sub-data slice line, the count value is stored in bits 3 to 7 of the clock run-in detect register 3 (address 0208 16 ). read out these bits after the occurence of a data slicer interrupt (refer to (11) interrupt request generating circuit). figure 36 shows the structure of clock run-in detect registers 1 and 3. 70 clock run-in count value of sub-data slice line clock run-in register 3 (cr3 : address 0209 16 ) data latch completion flag for caption data in sub-data slice line 0: data is not latched yet 1: data is latched data slice line selection bit for interrupt request 0: main data slice line 1: sub-data slice line interrupt mode selection bit 0: interrupt occurs at end of data slice line 1: interrupt occurs at completion of caption data latch ] when the count value in the window is 4 to 6, this is determined as a clock run-in. horizontal synchronizing signal composite video signal window clock run-in start bit data + 16-bit data time to be set in the window register time to be set in the start bit position register 70 number of reference clocks to be counted in one clock run-in pulse period clock run-in detect registers 1, 3 ( crd1 : address 00e8 16 ) ( crd3 : address 0208 16 ) test bits : read-only 70 clock run-in count value of main-data slice line clock run-in register 1 (cr1 : address 00e6 16 ) fix these bits to ?101 2 010 1
mitsubishi microcomputers m37271mf-xxxsp m37271ef-xxxsp, m37271efsp single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller 37 conditions for setting bit 4 of dsc3 to 1 data clock of 16 pulses has occured in sub-data slaice line data clock of 16 pulses has occured in sub-data slaice line and clock run-in pulse are detected 4 to 6 times (10) 16-bit shift register the caption data converted into a digital value by the comparator is stored into the 16-bit shift register in synchronization with the data clock. for the main data slice line, the contents of the high-order 8 bits of the stored caption data and the contents of the low-order 8 bits of the same data can be obtained by reading out the data register 2 (address 00e5 16 ) and data register 1 (address 00e4 16 ), respectively. for the sub-data slice line, the contents of the high-order 8 bits and the contents of the low-order 8 bits can be obtained by reading out the data register 4 (address 00ed 16 ) and the data register 3 (address 00ec 16 ), respectively. these registers are reset to 0 at a falling of v sep . read out data registers 1 and 2 after the occurence of a data slicer interrupt (refer to (11) interrupt request generating circuit). (11) interrupt request generating circuit the occurence sources of interrupt request are selected by combination of the following bits; bits 5 and 6 of the clock run-in register 3 (address 0209 16 ), bit 1 of the clock run-in register 2 (address 00e7 16 ) (refer to table 6). read out the contents of data registers 1 to 4 and the contents of bits 3 to 7 of the clock run-in detect registers 1 and 3 after the occurence of a data slicer interrupt request. for a data clock, 16 pulses are generated. when just 16 pulses have been generated, bit 7 of the data slicer control register is set to 1 (refer to figure 23). when method 1 is already selected as a start bit detecting method, this bit becomes a logical product (and) value with a clock run-in determination result by setting bit 7 of the start bit position register to 1. when method 2 is already selected as a start bit detecting method and 16 pulses are generated of a data clock regardless of bit 7 of the start bit position register, this bit is set to 1. the contents of this bit are reset at a falling of the vertical synchronizing signal (v sep ). table 4. setting conditions for caption data latch completion flag bit 7 of sp 0 1 conditions for setting bit 7 of dsc1 to 1 data clock of 16 pulses has occured in main data slaice line data clock of 16 pulses has occured in main data slaice line and clock run-in pulse are detected 4 to 6 times (9) data clock generating circuit this circuit generates a data clock phase-synchronized with the start bit detected in the start bit detecting circuit. set the time from detection of the start bit to occurrence of the data clock in bits 3 to 7 of the clock run-in detect register 2 (address 00e9 16 ). the time to be set is represented by the following expression: time = (13 + set value) 5 reference clock period slice line main data slice line sub-data slice line b5 0 1 sources at end of data slice line data clock of 16 pulses has occured and clock run-in pulse are detected 4 to 6 times data clock of 16 pulses has occured at end of data slice line data clock of 16 pulses has occured and clock run-in pulse are detected 4 to 6 times data clock of 16 pulses has occured b6 0 1 0 1 cr2 b1 0 1 0 1 0 1 0 1 cr3 table 5. occurence sources of interrupt request occurence souces of interrupt request
mitsubishi microcomputers m37271mf-xxxsp m37271ef-xxxsp, m37271efsp single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller 38 fig. 37. sync pulse counter register sync pulse counter register (syc : address 020f 16 ) count value count source count time 0: h sync signal 1: composite sync signal f(x in )/2 13 (1024 m s, f(x in ) = 8 mhz) 70 (12) synchronizing signal counter the synchronizing signal counter counts the composite sync signal taken out from a video signal in the data slicer circuit or the vertical synchronizing signal v sep as a count source. the count value in a certain time (t time) generated by f(x in )/2 13 or f(x in )/2 13 is stored into the 5-bit latch. accordingly, the latch value changes in the cycle of t time. when the count value exceeds 1f 16 , 1f 16 is stored into the latch. the latch value can be obtained by reading out the sync pulse counter register (address 020f 16 ). a count source is selected by bit 5 of the sync pulse counter register. the synchronizing signal counter is used when bit 0 of the pwm mode register 1 (address 02ea 16 ). figure 37 shows the structure of the sync pulse counter and figure 38 shows the synchronizing signal counter block diagram. fig. 38. synchronizing signal counter block diagram reset 5-bit counter latch (5 bits) f(x in )/2 13 composite sync signal h sync signal counter sync pulse counter register data bus selection gate : connected to black colored side when reset. b5
mitsubishi microcomputers m37271mf-xxxsp m37271ef-xxxsp, m37271efsp single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller 39 function in conformity with philips i 2 c-bus standard: 10-bit addressing format 7-bit addressing format high-speed clock mode standard clock mode in conformity with philips i 2 c-bus standard: master transmission master reception slave transmission slave reception 16.1 khz to 400 khz (at f = 4 mhz) table 6. multi-master i 2 c-bus interface functions item format communication mode scl clock frequency f : system clock = f(x in )/2 note: we are not responsible for any third partys infringement of patent rights or other rights attributable to the use of the con- trol function (bits 6 and 7 of the i 2 c control register at address 00f9 16 ) for connections between the i 2 c-bus interface and ports (scl1, scl2, sda1, sda2). multi-master i 2 c-bus interface the multi-master i 2 c-bus interface is a circuit for serial communica- tions conformed with the philips i 2 c-bus data transfer format. this interface, having an arbitration lost detection function and a synchro- nous function, is useful for serial communications of the multi-mas- ter. figure 39 shows a block diagram of the multi-master i 2 c-bus inter- face and table 6 shows multi-master i 2 c-bus interface functions. this multi-master i 2 c-bus interface consists of the i 2 c address reg- ister, the i 2 c data shift register, the i 2 c clock control register, the i 2 c control register, the i 2 c status register and other control circuits. fig. 39. block diagram of multi-master i 2 c-bus interface i c address register b7 b0 sad6 sad5 sad4 sad3 sad2 sad1 sad0 rbw noise elimination circuit serial data (sda) address comparator b7 i c data shift register b0 data control circuit i c clock control register system clock ( f ) interrupt generating circuit interrupt request signal (iicirq) b7 mst trx bb pin al aas ad0 lrb b0 i c status register s1 b7 b0 bsel1 bsel0 10bit sad als bc2 bc1 bc0 s1d i c clock control register bit counter bb circuit clock control circuit noise elimination circuit serial clock (scl) b7 b0 ack ack bit fast mode ccr4 ccr3 ccr2 ccr1 ccr0 internal data bus clock division s 0 s2 s0d al circuit es0 2 2 2 2 2
mitsubishi microcomputers m37271mf-xxxsp m37271ef-xxxsp, m37271efsp single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller 40 (1) i 2 c data shift register the i 2 c data shift register (s0 : address 00f6 16 ) is an 8-bit shift register to store receive data and write transmit data. when transmit data is written into this register, it is transferred to the outside from bit 7 in synchronization with the scl clock, and each time one-bit data is output, the data of this register are shifted one bit to the left. when data is received, it is input to this register from bit 0 in synchronization with the scl clock, and each time one-bit data is input, the data of this register are shifted one bit to the left. the i 2 c data shift register is in a write enable status only when the es0 bit of the i 2 c control register (address 00f9 16 ) is 1. the bit counter is reset by a write instruction to the i 2 c data shift register. when both the es0 bit and the mst bit of the i 2 c status register (address 00f8 16 ) are 1, the scl is output by a write instruction to the i 2 c data shift register. reading data from the i 2 c data shift regis- ter is always enabled regardless of the es0 bit value. note: to write data into the i 2 c data shift register after setting the mst bit to 0 (slave mode), keep an interval of 8 machine cycles or more. (2) i 2 c address register the i 2 c address register (address 00f7 16 ) consists of a 7-bit slave ___ address and a read /write bit. in the addressing mode, the slave ad- dress written in this register is compared with the address data to be received immediately after the start condition are detected. ____ n bit 0: read /write bit (rbw) not used in the 7-bit addressing mode. in the 10-bit addressing mode, the first address data to be received is compared with the contents (sad6 to sad0 + rbw) of the i 2 c address register. the rbw bit is cleared to 0 automatically when the stop condition is detected. n bits 1 to 7: slave address (sad0Csad6) these bits store slave addresses. regardless of the 7-bit address- ing mode and the 10-bit addressing mode, the address data trans- mitted from the master is compared with the contents of these bits. (3) i 2 c clock control register the i 2 c clock control register (address 00fa 16 ) is used to set ack control, scl mode and scl frequency. n bits 0 to 4: scl frequency control bits (ccr0Cccr4) these bits control the scl frequency. refer to table 7. n bit 5: scl mode specification bit (fast mode) this bit specifies the scl mode. when this bit is set to 0, the stan- dard clock mode is set. when the bit is set to 1, the high-speed clock mode is set. n bit 6: ack bit (ack bit) this bit sets the sda status when an ack clock ] is generated. when this bit is set to 0, the ack return mode is set and make sda l at the occurrence of an ack clock. when the bit is set to 1, the ack non-return mode is set. the sda is held in the h status at the oc- currence of an ack clock. however, when the slave address matches the address data in the reception of address data at ack bit = 0, the sda is automatically made l (ack is returned). if there is a mismatch between the slave address and the address data, the sda is automatically made h(ack is not returned). ] ack clock: clock for acknowledgement n bit 7: ack clock bit (ack) this bit specifies a mode of acknowledgment which is an acknowl- edgment response of data transmission. when this bit is set to 0, the no ack clock mode is set. in this case, no ack clock occurs after data transmission. when the bit is set to 1, the ack clock mode is set and the master generates an ack clock upon comple- tion of each 1-byte data transmission.the device for transmitting address data and control data releases the sda at the occurrence of an ack clock (make sda h) and receives the ack bit generated by the data receiving device. note: do not write data into the i 2 c clock control register during transmitting. if data is written during transmitting, the i 2 c clock generator is reset, so that data cannot be transmitted nor- mally. fig. 40. structure of i 2 c address register sad6 sad5 sad4 sad3 sad2 sad1 sad0 rbw slave address i 2 c address register (s0d: address 00f7 16 ) read/write bit 70
mitsubishi microcomputers m37271mf-xxxsp m37271ef-xxxsp, m37271efsp single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller 41 table 7. set values of i 2 c clock control register and scl frequency (4) i 2 c control register the i 2 c control register (address 00f9 16 ) controls data communica- tion format. n bits 0 to 2: bit counter (bc0Cbc2) these bits decide the number of bits for the next 1-byte data to be transmitted. an interrupt request signal occurs immediately after the number of bits specified with these bits are transmitted. when a start condition is received, these bits become 000 2 and the address data is always transmitted and received in 8 bits. n bit 3: i 2 c interface use enable bit (es0) this bit enables to use the multimaster i 2 c bus interface. when this bit is set to 0, the use disable status is provided, so the sda and the scl become high-impedance. when the bit is set to 1, use of the interface is enabled. when es0 = 0, the following is performed. ? pin = 1, bb = 0 and al = 0 are set (they are bits of the i 2 c status register at address 00f8 16 ). ? writing data to the i 2 c data shift register (address 00f6 16 ) is dis- abled. n bit 4: data format selection bit (als) this bit decides whether or not to recognize slave addresses. when this bit is set to 0, the addressing format is selected, so that ad- dress data is recognized. when a match is found between a slave address and address data as a result of comparison or when a gen- eral call (refer to (5) i 2 c status register, bit 1) is received, trans- mission processing can be performed. when this bit is set to 1, the free data format is selected, so that slave addresses are not recog- nized. n bit 5: addressing format selection bit (10bit sad) this bit selects a slave address specification format. when this bit is set to 0, the 7-bit addressing format is selected. in this case, only the high-order 7 bits (slave address) of the i 2 c address register (ad- dress 00f7 16 ) are compared with address data. when this bit is set to 1, the 10-bit addressing format is selected, all the bits of the i 2 c address register are compared with address data. n bits 6 and 7: connection control bits between i 2 c-bus interface and ports (bsel0, bsel1) these bits controls the connection between scl and ports or sda and ports (refer to figure 42). fig. 41. structure of i 2 c clock control register ack ack bit fast mode ccr4 ccr3 ccr2 ccr1 ccr0 i 2 c clock control register (s2 : address 00fa 16 ) 70 scl frequency control bits refer to table 7. scl mode specification bit 0 : standard clock mode 1 : high-speed clock mode ack bit 0 : ack is returned. 1 : ack is not returned. ack clock bit 0 : no ack clock 1 : ack clock scl frequency (at f = 4mhz, unit : khz) setting value of ccr4Cccr0 standard clock mode setting disabled setting disabled setting disabled setting disabled setting disabled 100 83.3 500/ccr value 17.2 16.6 16.1 high-speed clock mode setting disabled setting disabled setting disabled 333 250 400(note) 166 1000/ccr value 34.5 33.3 32.3 ccr4 0 0 0 0 0 0 0 1 1 1 ccr3 0 0 0 0 0 0 0 1 1 1 ccr2 0 0 0 0 1 1 1 1 1 1 ccr1 0 0 1 1 0 0 1 0 1 1 ccr0 0 1 0 1 0 1 0 1 0 1 note: at 400 khz in the high-speed clock mode, the duty is 40%. in the other cases, the duty is 50%.
mitsubishi microcomputers m37271mf-xxxsp m37271ef-xxxsp, m37271efsp single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller 42 fig. 43. structure of i 2 c control register 7 bsel1 bsel0 10 bit sad als es0 bc2 bc1 bc0 0 connection control bits between i 2 c-bus interface and ports b7 b6 connection port 0 0 : none 0 1 : scl1, sda1 1 0 : scl2, sda2 1 1 : scl1, sda1, scl2, sda2 i 2 c control register (s1d : address 00f9 16 ) bit counter (number of transmit/receive bits) b2 b1 b0 0 0 0 : 8 0 0 1 : 7 0 1 0 : 6 0 1 1 : 5 1 0 0 : 4 1 0 1 : 3 1 1 0 : 2 1 1 1 : 1 i 2 c-bus interface use enable bit 0 : disabled 1 : enabled data format selection bit 0 : addressing format 1 : free data format addressing format selection bit 0 : 7-bit addressing format 1 : 10-bit addressing format (5) i 2 c status register the i 2 c status register (address 00f8 16 ) controls the i 2 c-bus inter- face status. the low-order 4 bits are read-only bits and the high- order 4 bits can be read out and written to. n bit 0: last receive bit (lrb) this bit stores the last bit value of received data and can also be used for ack receive confirmation. if ack is returned when an ack clock occurs, the lrb bit is set to 0. if ack is not returned, this bit is set to 1. except in the ack mode, the last bit value of received data is input. the state of this bit is changed from 1 to 0 by execut- ing a write instruction to the i 2 c data shift register (address 00f6 16 ). n bit 1: general call detecting flag (ad0) this bit is set to 1 when a general call ] whose address data is all 0 is received in the slave mode. by a general call of the master device, every slave device receives control data after the general call. the ad0 bit is set to 0 by detecting the stop condition or start con- dition. ] general call: the master transmits the general call address 00 16 to all slaves. n bit 2: slave address comparison flag (aas) this flag indicates a comparison result of address data. 1 in the slave receive mode, when the 7-bit addressing format is selected, this bit is set to 1 in one of the following conditions. ? the address data immediately after occurrence of a start condition agrees with the slave address stored in the high-order 7 bits of the i 2 c address register (address 00f7 16 ). ? a general call is received. 2 in the slave reception mode, when the 10-bit addressing format is selected, this bit is set to 1 with the following condition. ? when the address data is compared with the i 2 c address register (8 bits consisted of slave address and rbw), the first bytes agree. 3 the state of this bit is changed from 1 to 0 by executing a write instruction to the i 2 c data shift register (address 00f6 16 ). fig. 42. connection port control by bsel0 and bsel1 ? ??bsel0 scl1/p1 1 scl2/p1 2 ? ??bsel1 ? ??bsel0 sda1/p1 3 sda2/p1 4 ? ??bsel1 multi-master i 2 c-bus interface scl sda note: when using multi-master i 2 c-bus interface, set bits 3 and 4 of the serial i/o mode register (address 0213 16 ) to 1.
mitsubishi microcomputers m37271mf-xxxsp m37271ef-xxxsp, m37271efsp single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller 43 n bit 3: arbitration lost ] detecting flag (al) in the master transmission mode, when the sda is made l by any other device, arbitration is judged to have been lost, so that this bit is set to 1. at the same time, the trx bit is set to 0, so that immedi- ately after transmission of the byte whose arbitration was lost is com- pleted, the mst bit is set to 0. in the case arbitration is lost during slave address transmission, the trx bit is set to 0 and the recep- tion mode is set. consequently, it becomes possible to receive and recognize its own slave address transmitted by another master de- vice. ] arbitration lost: the status in which communication as a master is disabled. n bit 4: i 2 c-bus interface interrupt request bit (pin) this bit generates an interrupt request signal. each time 1-byte data is transmitted, the state of the pin bit changes from 1 to 0. at the same time, an interrupt request signal occurs to the cpu. the pin bit is set to 0 in synchronization with a falling of the last clock (in- cluding the ack clock) of an internal clock and an interrupt request signal occurs in synchronization with a falling of the pin bit. when the pin bit is 0, the scl is kept in the 0 state and clock generation is disabled. figure 45 shows an interrupt request signal generating timing chart. the pin bit is set to 1 in one of the following conditions. ? executing a write instruction to the i 2 c data shift register (address 00f6 16 ). ? when the es0 bit is 0 ? at reset the conditions in which the pin bit is set to 0 are shown below: ? immediately after completion of 1-byte data transmission (includ- ing when arbitration lost is detected) ? immediately after completion of 1-byte data reception ? in the slave reception mode, with als = 0 and immediately after completion of slave address or general call address reception ? in the slave reception mode, with als = 1 and immediately after completion of address data reception n bit 5: bus busy flag (bb) this bit indicates the status of use of the bus system. when this bit is set to 0, this bus system is not busy and a start condition can be generated. when this bit is set to 1, this bus system is busy and the occurrence of a start condition is disabled by the start condi- tion duplication prevention function (note). this flag can be written by software only in the master transmission mode. in the other modes, this bit is set to 1 by detecting a start condition and set to 0 by detecting a stop condition. when the es0 bit of the i 2 c control register (address 00f9 16 ) is 0 and at reset, the bb flag is kept in the 0 state. n bit 6: communication mode specification bit (transfer direction specification bit: trx) this bit decides a direction of transfer for data communication. when this bit is 0, the reception mode is selected and the data of a trans- mitting device is received. when the bit is 1, the transmission mode is selected and address data and control data are output onto the sda in synchronization with the clock generated on the scl. when the als bit of the i 2 c control register (address 00f9 16 ) is 0 in the slave reception mode is selected, the trx bit is set to 1 __ (transmit) if the least significant bit (r/w bit) of the address data trans- __ mitted by the master is 1. when the als bit is 0 and the r/w bit is 0, the trx bit is cleared to 0 (receive). the trx bit is cleared to 0 in one of the following conditions. ? when arbitration lost is detected. ? when a stop condition is detected. ? when occurence of a start condition is disabled by the start condition duplication preventing function (note). ? with mst = 0 and when a start condition is detected. ? with mst = 0 and when ack non-return is detected. ? at reset n bit 7: communication mode specification bit (master/slave speci- fication bit: mst) this bit is used for master/slave specification for data communica- tion. when this bit is 0, the slave is specified, so that a start condition and a stop condition generated by the master are re- ceived, and data communication is performed in synchronization with the clock generated by the master. when this bit is 1, the master is specified and a start condition and a stop condition are gener- ated, and also the clocks required for data communication are gen- erated on the scl. the mst bit is cleared to 0 in one of the following conditions. ? immediately after completion of 1-byte data transmission when ar- bitration lost is detected ? when a stop condition is detected. ? when occurence of a start condition is disabled by the start condition duplication preventing function (note). ? at reset note: the start condition duplication prevention function disables the occurence of a start condition, reset of bit counter and scl output when the following condition is satisfied: ? a start condition is set by another master device.
mitsubishi microcomputers m37271mf-xxxsp m37271ef-xxxsp, m37271efsp single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller 44 7 mst 0 i 2 c status register (s1 : address 00f8 16 ) last receive bit (note) 0 : last bit = ?? 1 : last bit = ?? general call detecting flag (note) 0 : no general call detected 1 : general call detected slave address comparison flag (note) 0 : address disagreement 1 : address agreement arbitration lost detecting flag (note) 0 : not detected 1 : detected i 2 c-bus interface interrupt request bit 0 : interrupt request issued 1 : no interrupt request issued bus busy flag 0 : bus free 1 : bus busy communication mode specification bits 00 : slave receive mode 01 : slave transmit mode 10 : master receive mode 11 : master transmit mode trx bb pin al aas ad0 lrb note: these bit and flags can be read out but cannot be written. (6) start condition generating method when the es0 bit of the i 2 c control register (address 00f9 16 ) is 1, execute a write instruction to the i 2 c status register (address 00f8 16 ) for setting the mst, trx and bb bits to 1. then a start condi- tion occurs. after that, the bit counter becomes 000 2 and an scl for 1 byte is output. the start condition generating timing and bb bit set timing are different in the standard clock mode and the high- speed clock mode. refer to figure 46, the start condition generat- ing timing diagram, and table 8, the start condition/stop condi- tion generating timing table. (7) stop condition generating method when the es0 bit of the i 2 c control register (address 00f9 16 ) is 1, execute a write instruction to the i 2 c status register (address 00f8 16 ) for setting the mst bit and the trx bit to 1 and the bb bit to 0. then a stop condition occurs. the stop condition generating tim- ing and the bb flag reset timing are different in the standard clock mode and the high-speed clock mode. refer to figure 47, the stop condition generating timing diagram, and table 8, the start condi- tion/stop condition generating timing table. table 8. start condition/stop condition generating timing table fig. 46. start condition generating timing diagram fig. 47. stop condition generating timing diagram fig. 45. interrupt request signal generating timing fig. 44. structure of i 2 c status register scl pin iicirq i 2 c status register write signal set time for bb flag aaa hold time setup time scl sda bb flag setup time i 2 c status register write signal reset time for bb flag aaa aaa hold time setup time scl sda bb flag item setup time hold time set/reset time for bb flag standard clock mode 5.0 m s (20 cycles) 5.0 m s (20 cycles) 3.0 m s (12 cycles) high-speed clock mode 2.5 m s (10 cycles) 2.5 m s (10 cycles) 1.5 m s (6 cycles) note: absolute time at f = 4 mhz. the value in parentheses de- notes the number of f cycles.
mitsubishi microcomputers m37271mf-xxxsp m37271ef-xxxsp, m37271efsp single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller 45 fig. 48. start condition/stop condition detecting timing diagram (8) start/stop condition detecting condi- tions the start/stop condition detecting conditions are shown in fig- ure 48 and table 9. only when the 3 conditions of table 9 are satis- fied, a start/stop condition can be detected. note: when a stop condition is detected in the slave mode (mst = 0), an interrupt request signal iicirq occurs to the cpu. (9) address data communication there are two address data communication formats, namely, 7-bit addressing format and 10-bit addressing format. the respective ad- dress communication formats is described below. 1 7-bit addressing format to meet the 7-bit addressing format, set the 10bit sad bit of the i 2 c control register (address 00f9 16 ) to 0. the first 7-bit address data transmitted from the master is compared with the high-order 7-bit slave address stored in the i 2 c address register (address 00f7 16 ). at the time of this comparison, address comparison of the rbw bit of the i 2 c address register (address 00f7 16 ) is not made. for the data transmission format when the 7-bit address- ing format is selected, refer to figure 49, (1) and (2). 2 10-bit addressing format to meet the 10-bit addressing format, set the 10bit sad bit of the i 2 c control register (address 00f9 16 ) to 1. an address compari- son is made between the first-byte address data transmitted from the master and the 7-bit slave address stored in the i 2 c address register (address 00f7 16 ). at the time of this comparison, an ad- dress comparison between the rbw bit of the i 2 c address regis- __ ter (address 00f7 16 ) and the r/w bit which is the last bit of the address data transmitted from the master is made. in the 10-bit __ addressing mode, the r/w bit which is the last bit of the address data not only specifies the direction of communication for control data but also is processed as an address data bit. aaa aaa hold time setup time scl sda (start condition) sda (stop condition) scl release time aaa aaa hold time setup time standard clock mode 6.5 m s (26 cycles) < scl release time 3.25 m s (13 cycles) < setup time 3.25 m s (13 cycles) < hold time high-speed clock mode 1.0 m s (4 cycles) < scl release time 0.5 m s (2 cycles) < setup time 0.5 m s (2 cycles) < hold time table 9. start condition/stop condition detecting conditions note: absolute time at f = 4 mhz. the value in parentheses de- notes the number of f cycles. fig. 49. address data communication format s slave address a data a data a/a p r/w 7 bits ? 1 to 8 bits 1 to 8 bits s slave address a data a data ap 7 bits ? 1 to 8 bits 1 to 8 bits (1) a master-transmitter transmits data to a slave-receiver s slave address 1st 7 bits a a data 7 bits ? 8 bits 1 to 8 bits (2) a master-receiver receives data from a slave-transmitter slave address 2nd byte a data a/a p 1 to 8 bits s slave address 1st 7 bits a a 7 bits ? 8 bits 7 bits (3) a master-transmitter transmits data to a slave-receiver with a 10-bit address slave address 2nd byte data 1 to 8 bits sr slave address 1st 7 bits a data ap 1 to 8 bits ? (4) a master-receiver receives data from a slave-transmitter with a 10-bit address s : start condition p : stop condition a : ack bit r/w : read/write bit sr : restart condition from master to slave from slave to master a r/w r/w r/w r/w
mitsubishi microcomputers m37271mf-xxxsp m37271ef-xxxsp, m37271efsp single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller 46 when the first-byte address data matches the slave address, the aas bit of the i 2 c status register (address 00f8 16 ) is set to 1. after the second-byte address data is stored into the i 2 c data shift register (address 00f6 16 ), make an address comparison between the sec- ond-byte data and the slave address by software. when the address data of the 2 bytes matches the slave address, set the rbw bit of the i 2 c address register (address 00f7 16 ) to 1 by software. this pro- __ cessing can match the 7-bit slave address and r/w data, which are received after a restart condition is detected, with the value of the i 2 c address register (address 00f7 16 ). for the data transmission format when the 10-bit addressing format is selected, refer to figure 49, (3) and (4). (10) example of master transmission an example of master transmission in the standard clock mode, at the scl frequency of 100 khz and in the ack return mode is shown below. 1 set a slave address in the high-order 7 bits of the i 2 c address register (address 00f7 16 ) and 0 in the rbw bit. 2 set the ack return mode and scl = 100 khz by setting 85 16 in the i 2 c clock control register (address 00fa 16 ). 3 set 10 16 in the i 2 c status register (address 00f8 16 ) and hold the scl at the h level. 4 set a communication enable status by setting 48 16 in the i 2 c control register (address 00f9 16 ). 5 set the address data of the destination of transmission in the high- order 7 bits of the i 2 c data shift register (address 00f6 16 ) and set 0 in the least significant bit. 6 set f0 16 in the i 2 c status register (address 00f8 16 ) to generate a start condition. at this time, an scl for 1 byte and an ack clock automatically occurs. 7 set transmit data in the i 2 c data shift register (address 00f6 16 ). at this time, an scl and an ack clock automatically occurs. 8 when transmitting control data of more than 1 byte, repeat step 7 . 9 set d0 16 in the i 2 c status register (address 00f8 16 ). after this, if ack is not returned or transmission ends, a stop condition occurs. (11) example of slave reception an example of slave reception in the high-speed clock mode, at the scl frequency of 400 khz, in the ack non-return mode and using the addressing format is shown below. 1 set a slave address in the high-order 7 bits of the i 2 c address register (address 00f7 16 ) and 0 in the rbw bit. 2 set the no ack clock mode and scl = 400 khz by setting 25 16 in the i 2 c clock control register (address 00fa 16 ). 3 set 10 16 in the i 2 c status register (address 00f8 16 ) and hold the scl at the h level. 4 set a communication enable status by setting 48 16 in the i 2 c control register (address 00f9 16 ). 5 when a start condition is received, an address comparison is made. 6 ?when all transmitted addresses are 0 (general call) ad0 of the i 2 c status register (address 00f8 16 ) is set to 1 and an interrupt request signal occurs. ?when the transmitted addresses match the address set in 1 ass of the i 2 c status register (address 00f8 16 ) is set to 1 and an interrupt request signal occurs. ?in the cases other than the above ad0 and aas of the i 2 c status register (address 00f8 16 ) are set to 0 and no interrupt request signal occurs. 7 set dummy data in the i 2 c data shift register (address 00f6 16 ). 8 when receiving control data of more than 1 byte, repeat step 7 . 9 when a stop condition is detected, the communication ends.
mitsubishi microcomputers m37271mf-xxxsp m37271ef-xxxsp, m37271efsp single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller 47 osd mode (on-screen display mode) 40 characters 5 16 lines 16 5 20 dots 14 kinds 5 1, 5 2, 5 3 1t c 5 1/2h, 1t c 5 1h, 1.5t c 5 1/2h, 1.5t c 5 1h, 2t c 5 2h, 3t c 5 3h border 1 screen : 7 kinds, max. 15 kinds (a character unit) possible (a screen unit, 1 screen : 7 kinds, max. 7 kinds) possible (a character unit, 1 screen : 7 kinds, max. 7 kinds) possible (a screen unit, 1 screen : 7 kinds, max. 7 kinds) r, g, b, i1, out1, out2 dual layer osd function (layer 2) possible osd functions table 10 outlines the osd functions of the m37271mf-xxxsp. the m37271mf-xxxsp incorporates an osd control circuit of 40 characters 5 16 lines. osd is controlled by the osd control regis- ter. there are 3 display modes and they are selected by a block unit. the display modes are selected by the block control register i (i = 1 to 6). the features of each mode are described below. exosd mode (extra on-screen display mode) 40 characters 5 16 lines 16 5 26 dots 6 kinds 5 1, 5 2, 5 3 1t c 5 1/2h, 1t c 5 1h border, extra font (32 kinds) 1 screen : 7 kinds, max. 7 kinds (a character unit) possible (a screen unit, 1 screen : 7 kinds, max. 7 kinds) possible (a character unit, 1 screen : 7 kinds, max. 7 kinds) possible (a screen unit, 1 screen : 7 kinds, max. 7 kinds) possible (a screen unit, 1 screen : 7 kinds, max. 7 kinds) r, g, b, i1, i2, out1, out2 possible cc mode (closed caption mode) 40 characters 5 16 lines 16 5 26 dots (character : 20 5 16 dots) 2 kinds 5 1, 5 2 1t c 5 1/2h smooth italic, under line, flash 1 screen : 7 kinds, max. 7 kinds (a character unit) possible (a screen unit, 1 screen : 7 kinds, max. 7 kinds) possible (a character unit, 1 screen : 7 kinds, max. 7 kinds) r, g, b, out1, out2 auto solid space function window function dual layer osd function (layer 1) possible parameter number of display characters dot structure kinds of characters kinds of character sizes attribute character font coloring raster coloring character background coloring border coloring extra font coloring osd output function display expansion (multiline display) pre-divide ratio (note) dot size table 10. features of each display mode display mode 320 kinds (in exosd mode, they can be combined with 32 kinds of extra fonts) notes 1: the divide ratio of the frequency divider (the pre-divide circuit) is referred as pre-divide ratio hereafter. 2: the character size is specified with dot size and pre-divide ratio (refer to (3) dote size).
mitsubishi microcomputers m37271mf-xxxsp m37271ef-xxxsp, m37271efsp single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller 48 the osd circuit has an extended display mode. this mode allows multiple lines (16 lines or more) to be displayed on the screen by interrupting the display each time one line is displayed and rewriting data in the block for which display is terminated by software. figure 50 shows the configuration of osd character. figure 51 shows the block diagram of the osd control circuit. figure 52 shows the structure of the osd control register. figure 53 shows the structure of the block control register. fig. 50. configuration of osd character 16 dots 26 dots 20 dots underline area + blank area + : displayed only in ccd mode. blank area 26 dots 20 dots character font 26 dots 20 dots osd mode cc mode extra font exosd mode 16 dots 16 dots 16 dots 16 dots logical sum (or) + +
mitsubishi microcomputers m37271mf-xxxsp m37271ef-xxxsp, m37271efsp single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller 49 fig. 51. block diagram of osd control circuit display oscillation circuit osc1 osc2 h sync v sync ram for osd 20-bit 5 40 5 16 data bus ram for osd (16-bit 5 20 5 320) + 16-bit 5 26 5 32) shift register 2 16-bit shift register 1 16-bit data slicer clock clock for osd output circuit r g b i1 i2 osd control circuit out1 out2 control registers for osd (address 00ce 16 ) (address 00cf 16 ) (addresses 00d0 16 to 00df 16 ) (address 0216 16 ) (address 0217 16 ) (address 0218 16 ) (address 0219 16 ) (address 021b 16 ) (addresses 021c 16 to 021f 16 ) (addresses 0220 16 to 023f 16 ) osd control register horizontal position register block control registers clock source control register i/o polarity control register raster color register extra font color register border color register window h/l registers vertical registers
mitsubishi microcomputers m37271mf-xxxsp m37271ef-xxxsp, m37271efsp single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller 50 flash mode selection bit 0 : color signal of character background part does not flash 1 : color signal of character background part flashes 70 osd control register (oc : address 00ce 16 ) osd control bit (note 1) 0 : all-blocks display off 1 : all-blocks display on scan mode selection bit 0 : normal scan mode 1 : bi-scan mode border type selection bit 0 : all bordered 1 : shadow bordered (note 2) automatic solid space control bit 0 : off 1 : on window control bit 0 : off 1 : on layer mixing control bits (note 3) b7 b6 0 0 : logical sum (or) of layer 1? color and layer 2? color 0 1 : layer 1? color has priority 1 0 : layer 2? color has priority 1 1 : do not set notes 1 : even this bit is switched during display, the display screen remains unchanged until a rising (falling) of the next v sync . 2 : shadow border is output at right and bottom side of the font. 3 : set ?0?during displaying extra fonts. display layer layer 1 layer 2 dot size 1t c 5 1/2h 1t c 5 1h 2t c 5 2h 3t c 5 3h 1t c 5 1/2h 1t c 5 1h 2t c 5 2h 3t c 5 3h 1t c 5 1/2h 1t c 5 1h 2t c 5 2h 3t c 5 3h 1t c 5 1/2h 1t c 5 1h 1t c 5 1/2h 1t c 5 1h 1.5t c 5 1/2h 1.5t c 5 1h b3 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 b4 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 b6 0 0 1 1 1 table 11. setting value of block control registers pre-divide ratio 5 1 5 2 5 3 5 1 5 2 b5 0 1 0 1 1 cs 6 0 1 notes 1: cs 6 : bit 6 of clock control register (address 0216 16 ) 2: t c : osd clock cycle divided in the pre-divide circuit 3: h: h sync 70 block control register i (i = 1 to 16) (bci : addresses 00d0 16 to 00df) display mode selection bits b1 b0 0 0 : display off 0 1 : osd mode 1 0 : cc mode 1 1 : exosd mode border control bit 0 : border off 1 : border on notes : bit 4 of the color code 1 controls out1 output when bit 7 is ?. bit 4 of the color code 1 controls out2 output when bit 7 is ?. dot size selection bit refer to table 11. pre-divide ratio e layer selection bits refer to table 11. out 2 output control bit (note) 0 : out2 output off 1 : out2 output on fig. 53. structure of block control registers fig. 52. structure of osd control register
mitsubishi microcomputers m37271mf-xxxsp m37271ef-xxxsp, m37271efsp single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller 51 osd mode same as layer 1 same as layer 1 (note) pre-divide ratio = 1 pre-divide ratio = 2 1t c 5 1/2h 1t c 5 1/2h, 1.5t c 5 1/2h 1t c 5 1h 1t c 5 1h, 1.5t c 5 1h same position as layer 1 (1) dual layer osd m37271mf-xxxsp has 2 layers; layer 1 and layer 2. these layers display the osd for controlling tv and the closed caption display at the same time and overlayed on each other. each block can be assigned to either layer by bits 6 and 5 of the block control register (refer to figure 53). for example, only when both bits 5 and 6 are 1, the block is assigned to layer 2. other bit combinations assign the block to layer 1. when a block of layer 1 is overlapped with that of layer 2, a screen is combined (refer to figure 55) by bits 7 and 6 of the osd control register (refer to figure 52). note: when using the dual layer osd, note table 12. fig. 54. image of dual layer osd cc mode data slicer clock or osc1 5 1 or 5 2 (all blocks) 1t c 5 1/2h arbitrary display mode osd clock source pre-divide ratio dot size horizontal display start position table 12. conditions of dual layer note: for the pre-divide ratio of the layer 2, select the same as the layer 1s ratio by bit 6 of the clock control register. block in layer 1 block in layer 2 fig. 55. display example of dual layer osd layer 2 layer 1 block 1 block 2 block 11 block 12 ... block 13 block 14 block 15 block 16 block block display example of layer 1 = ?ello,?layer 2 = ?h5 ch5 hello logical sum (or) of layer 1? color and layer 2? color bit 7 = ?,?bit 6 = ? layer 1? color has priority bit 7 = ?? bit 6 = ? ch5 hello layer 2? color has priority bit 7 = ?,?bit 6 = ? hello ch5 block parameter
mitsubishi microcomputers m37271mf-xxxsp m37271ef-xxxsp, m37271efsp single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller 52 (2) display position the display positions of characters are specified in units called a block. there are 16 blocks, blocks 1 to 16. up to 40 characters can be displayed in each block (refer to (6) memory for osd). the display position of each block can be set in both horizontal and vertical directions by software. the display position in the horizontal direction can be selected for all blocks in common from 256-step display positions in units of 4 t osc (t osc = oscillating cycle for osd). the display position in the vertical direction for each block can be selected from 1024-step display positions in units of 1 t h ( t h = h sync cycle). blocks are displayed in conformance with the following rules: 1 when the display position is overlapped with another block (figure 56, (b)), a lower block number (1 to 16) is displayed on the front. 2 when another block display position appears while one block is displayed (figure 56 (c)), the block with a larger set value as the vertical display start position is displayed. however, do not dis- play block with the dot size of 2t c 5 2h or 3t c 5 3h during dis- play period ( ] ) of another block. ] in the case of osd mode block: 20 dots in vertical from the verti- cal display start position. ] in the case of ccd or exosd mode block: 26 dots in vertical from the vertical display start position. fig. 56. display position (hr) vp12, vp22 block 1 block 2 (a) example when each block is separated vp13, vp23 block 3 (hr) vp11, vp21 vp12, vp22 block 1 (b) example when block 3 overlaps with block 1 (block 3 is not displayed) (hr) vp11, vp21 vp12, vp22 (c) example when block 3 overlaps in process of block 1 block 1 block 3 note: vp1i or vp2i (i : 1 to 6) indicates the contents of vertical position registers 1i or 2i. vp11, vp21
mitsubishi microcomputers m37271mf-xxxsp m37271ef-xxxsp, m37271efsp single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller 53 the display position in the vertical direction is determined by count- ing the horizontal sync signal (h sync ). at this time, it starts to count the rising edge (falling edge) of h sync signal from after about 1 ma- chine cycle of rising edge (falling edge) of v sync signal. so interval from rising edge (falling edge) of v sync signal to rising edge (falling edge) of h sync signal needs enough time (2 machine cycles or more) for avoiding jitter. the polarity of h sync and v sync signals can se- lect with the i/o polarity control register (address 0217 16 ). for de- tails, refer to (15) osd output pin control. note: when bits 0 and 1 of the i/o polarity control register (address 0217 16 ) are set to 1 (negative polarity), the vertical position is determined by counting falling edge of h sync signal after rising edge of v sync control signal in the microcomputer (re- fer to figure 57). fig. 57. supplement explanation for display position the vertical position for each block can be set in 1024 steps (where each step is 1t h (t h : h sync cycle)) as values 00 16 to ff 16 in vertical position register 1i (i = 1 to 16) (addresses 0220 16 to 022f 16 ) and values 00 16 to ff 16 in the vertical position register 2i (i = 1 to 16) (addresses 0230 16 to 023f 16 ). the structure of the vertical posi- tion registers is shown in figure 58. fig. 58. structure of vertical position registers the horizontal position is common to all blocks, and can be set in 256 steps (where 1 step is 4t c , t c being the oscillating cycle for display) as values 00 16 to ff 16 in bits 0 to 7 of the horizontal position register (address 00cf 16 ). the structure of the horizontal position register is shown in figure 59. fig. 59. structure of horizontal position register when bits 0 and 1 of the i/o polarity control register (address 0217 16 ) are set to ??(negative polarity) v sync signal input v sync control signal in microcomputer 0.25 to 0.50 [ m s] ( at f(x in ) = 8mhz) period of counting h sync signal (note 1) h sync signal input not count 12345 notes 1 : do not generate falling edge of h sync signal near rising edge of v sync control signal in microcomputer to avoid jitter. 2 : the pulse width of v sync and h sync needs 8 machine cycles or more. 70 vertical position register 1i (i = 1 to 16) (vp1i : addresses 0220 16 to 022f 16 ) control bits of vertical display start positions (note) vertical display start positions (low-order 8 bits) t h 5 (setting value of low-order 2 bits of vp2i 5 16 + setting value of low-order 4 bits of vp1i 5 16 + setting value of low-order 4 bits of vp1i 5 16 ) note : set values except ?0 16 ?and ?1 16 ?to vp1i when vp2i is ?0 16. 2 1 0 70 vertical position register 2i (i = 1 to 16) (vp2i : addresses 0230 16 to 023f 16 ) control bits of vertical display start positions (note) vertical display start positions (high-order 2 bits) t h 5 (setting value of low-order 2 bits of vp2i 5 16 + setting value of low-order 4 bits of vp1i 5 16 + setting value of low-order 4 bits of vp1i 5 16 ) 2 1 0 note : the setting value synchronizes with a rising (falling) of the v sync . 70 horizontal position register (hp : address 00cf 16 ) control bits of horizontal display start positions horizontal display start positions 4t osc 5 (setting value of high-order 4 bits 5 16 + setting value of low-order 4 bits 5 16 ) 1 0
mitsubishi microcomputers m37271mf-xxxsp m37271ef-xxxsp, m37271efsp single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller 54 notes 1 : 1t c (t c : osd clock cycle divided by prescaler) gap oc- curs between the horizontal display start position set by the horizontal position register and the most left dot of the 1st block. accordingly, when 2 blocks have different pre- divide ratios, their horizontal display start position will not match. 2 : the horizontal start position is based on the osd clock source cycle selected for each block. accordingly, when 2 blocks have different osd clock source cycles, their hori- zontal display start position will not match. fig. 60. notes on horizontal display start position (3) dot size the dot size can be selected by a block unit. the dot size in vertical direction is determined by dividing h sync in the vertical dot size con- trol circuit. the dot size in horizontal is determined by dividing the following clock in the horizontal dot size control circuit : the clock gained by dividing the osd clock source (data slicer clock, osc1) in the pre-divide circuit. the clock cycle divided in the pre-divide circuit is defined as 1t c . the dot size of the layer 1 is specified by bits 6 to 3 of the block control register. the dot size of the layer 2 is specified by the following bits : bits 3 and 4 of the block control register, bit 6 of the clock source control register. refer to figure 53 (the structure of the block control regis- ter), refer to figure 62 (the structure of the clock source control reg- ister). the block diagram of dot size control circuit is shown in figure 61. notes 1 : the pre-divide ratio = 3 cannot be used in the cc mode. 2 : the pre-divide ratio of the osd mode block on the layer 2 must be same as that of the cc mode block on the layer 1 by bit 6 of the clock source control register. 3 : in the bi-scan mode, the dot size in the vertical direction is 2 times as compared with the normal mode. refer to (13) scan mode about the scan mode. fig. 61. block diagram of dot size control circuit h sync 1t c 1t c block 1 (pre-divide ratio 1, clock source data slicer clock) 1t c 1t c 4t osc 5 n 4t osc 5 n note 1 note 2 block 2 (pre-divide ratio 2, clock source data slicer clock) block 3 (pre-divide ratio 3, clock source data slicer clock) block 4 (pre-divide ratio 3, clock source osc1) data slicer clock h sync osc1 cs 0 synchronization cycle 5 2 circuit cycle 5 3 pre-divide circuit clock cycle = 1t c horizontal dot size control circuit vertical dot size control circuit osd control circuit = = == = = ==
mitsubishi microcomputers m37271mf-xxxsp m37271ef-xxxsp, m37271efsp single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller 55 input port 1 0 1 (4) clock for osd as a clock for display to be used for osd, it is possible to select one of the following 3 types. ? data slicer clock output from the data slicer (approximately 26 mhz) ? clock from the lc oscillator supplied from the pins osc1 and osc2 ? clock from the ceramic resonator or the quartz-crystal oscillator from the pins osc1 and osc2 this osd clock for each block can be selected by the following bits : bit 7 of the port p3 direction register, bits 5 and 4 of the clock source control register (addresses 0216 16 ). a variety of character sizes can be obtained by combining dot sizes with osd clocks. when not us- ing the pins osc1 and osc2 for the osd clock i/o pins, the pins can be used as sub-clock i/o pins or port p6. fig. 63. block diagram of osd selection circuit fig. 62. structure of clock control register table 13. setting for p6 3 /osc1/x cin , p6 4 /osc2/x cout b7 port p3 direction register clock source control register osd clock i/o pin 0 011 101 b5 b4 sub-clock i/o pin 0 0 0 function register note : be sure to set bit 7 to ??for program of the mask and the eprom versions. for the emulator mcu version (m37270erss), be sure to set bit 7 to ??when using the data slicer clock for software debugging. 70 clock source control register (cs : address 0216 16 ) cc mode clock selection bit 0 : data slicer clock 1 : osc1 clock osd mode clock selection bits b2 b1 0 0 : data slicer clock 0 1 : osc1 clock 1 0 : 1 1 : do not set exosd mode clock selection bit 0 : data slicer clock 1 : osc1 clock pre-divide ratio of layer 2 selection bit 0 : 5 1 1 : 5 2 test bit (note) osd1 oscillating mode selection bits b5 b4 0 0 : 32 kh z oscillating mode 0 1 : input ports p6 3 , p6 4 1 0 : lc oscillating mode 1 1 : ceramic ?quartz-crystal oscillating mode ? ?1 ?0 ? ? 32 kh z data slicer circuit data slicer clock osc1 clock lc ceramic quartz-crystal oscillating mode for osd cs 5 , cs 4 ?0 ? ? ? cs 0 cs 1 cs 3 cs 2 = ? cc mode block osd mode block exosd mode block
mitsubishi microcomputers m37271mf-xxxsp m37271ef-xxxsp, m37271efsp single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller 56 (5) field determination display to display the block with vertical dot size of 1/2h, whether an even field or an odd field is determined through differences in a synchro- nizing signal waveform of interlacing system. the dot line 0 or 1 (re- fer to figure 65) corresponding to the field is displayed alternately. in the following, the field determination standard for the case where both the horizontal sync signal and the vertical sync signal are nega- tive-polarity inputs will be explained. a field determination is deter- mined by detecting the time from a falling edge of the horizontal sync signal until a falling edge of the v sync control signal (refer to figure 57) in the microcomputer and then comparing this time with the time of the previous field. when the time is longer than the comparing time, it is regarded as even field. when the time is shorter, it is re- garded as odd field the contents of this field can be read out by the field determination flag (bit 7 of the i/o polarity control register at address 0217 16 ). a dot line is specified by bit 6 of the i/o polarity control register (refer to figure 65). however, the field determination flag read out from the cpu is fixed to 0 at even field or 1 at odd field, regardless of bit 6. fig. 64. structure of i/o polarity control register 0 7 i/o polarity control register (pc : address 0217 16 ) h sync input polarity switch bit 0 : positive polarity input 1 : negative polarity input out2 output polarity switch bit 0 : positive polarity output 1 : negative polarity output v sync input polarity switch bit 0 : positive polarity input 1 : negative polarity input r/g/b output polarity switch bit 0 : positive polarity output 1 : negative polarity output i1, i2 output polarity switch bit 0 : positive polarity output 1 : negative polarity output out1 output polarity switch bit 0 : positive polarity output 1 : negative polarity output display dot line selection bit (note) field determination flag 0 : even field 1 : odd field note : refer to figure 65. at odd field at odd field 1 : at even field 0 : at even field
mitsubishi microcomputers m37271mf-xxxsp m37271ef-xxxsp, m37271efsp single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller 57 fig. 65. relation between field determination flag and display font both h sync signal and v sync signal are negative-polarity input field even odd field determination flag(note) display dot line selection bit display dot line 0 (t2 > t1) 1 (t3 < t2) 0 1 0 1 when using the field determination flag, be sure to set bit 0 of the pwm mode register 1 (address 020a 16 ) to 0. t2 t3 character rom font configuration diagram dot line 0 dot line 1 odd dot line 0 dot line 1 (nC1) field (odd-numbered) t1 0.25 to 0.50[ms] at f(x in ) = 8 mhz cc mode exosd mode 13579111315 1 3 5 7 9 11 13 15 17 19 21 23 25 26 24 22 20 18 16 14 12 10 8 6 4 2 2 4 6 8 10 12 14 16 1 3 5 7 9 11 13 15 17 19 20 18 16 14 12 10 8 6 4 2 13579111315 2 4 6 8 10 12 14 16 osd mode h sync v sync and v sync control signal in microcom- puter upper : v sync signal lower : v sync control signal in micro- computer (n) field (even-numbered) (n+1) field (odd-numbered) when the display dot line selection bit is 0, the font is displayed at even field, the font is displayed at odd field. bit 7 of the i/o polarity control register can be read as the field determination flag : 1 is read at odd field, 0 is read at even field. note : the field determination flag changes at a rising edge of the v sync control signal (negative-polarity input) in the microcomputer.
mitsubishi microcomputers m37271mf-xxxsp m37271ef-xxxsp, m37271efsp single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller 58 (6) memory for osd there are 2 types of memory for osd : rom for osd (addresses 10800 16 to 1567f 16 , 18000 16 to 1e43f 16 ) used to store character dot data (masked) and ram for osd (addresses 0800 16 to 0fff 16 ) used to specify the characters and colors to be displayed. the fol- lowing describes each type of memory. 1 1 1 1 1 rom for osd (addresses 10800 16 to 1567f 16 , 18000 16 to 1e43f 16 ) the rom for osd contains dot pattern data for characters to be displayed. to actually display the character code and the extra code stored in this rom, it is necessary to specify them by writing the character code inherent to each character (code determined based on the addresses in the rom for osd) into the ram for osd. the osd rom of the character font has a capacity of 12800 bytes. since 40 bytes are required for 1 character data, the rom can stores up to 320 kinds of characters. the osd rom of the extra font has a capacity of 1664 bytes. since 52 bytes are required for 1 character data, the rom can stores up to 32 kinds of characters. data of the character font and extra font is specified shown in figure 66. fig. 66. osd character data storing form osd rom address of character font data ad16 ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 line number character code font bit 02 16 to 15 16 00 16 to 13f 16 0 : left font 1 : right font osd rom address bit line number/character code/font bit 10 line number character code font bit ad16 ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 11 00 00 02 16 0000 16 7ff0 16 7ff8 16 601c 16 600c 16 600c 16 600c 16 600c 16 09 16 03 16 04 16 05 16 06 16 07 16 08 16 0a 16 601c 16 7ff8 16 7ff0 16 6300 16 6380 16 61c0 16 60e0 16 6070 16 11 16 0b 16 0c 16 0d 16 0e 16 0f 16 10 16 6038 16 601c 16 600c 16 0000 16 15 16 12 16 13 16 14 16 b0 b7 b0 b7 02 16 0003 16 0003 16 0003 16 0003 16 0003 16 0003 16 0003 16 0003 16 09 16 03 16 04 16 05 16 06 16 07 16 08 16 0a 16 0003 16 0003 16 0003 16 0003 16 0003 16 0003 16 0003 16 0003 16 11 16 0b 16 0c 16 0d 16 00 16 00 16 10 16 0003 16 0003 16 0003 16 0003 16 15 16 12 16 13 16 14 16 b0 b7 b0 b7 ffff 16 fffe 16 0000 16 0000 16 19 16 16 16 17 16 18 16 00 16 01 16 fffe 16 ffff 16 line number line number extra code font bit 00 16 to 19 16 00 16 to 1f 16 0 : left font 1 : right font osd rom address bit line number/extra code /font bit extra code line number left font right font line number data in osd rom left font right font data in osd rom osd rom address of extra font data character font extra font font bit = = = = = =
mitsubishi microcomputers m37271mf-xxxsp m37271ef-xxxsp, m37271efsp single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller 59 character code specification 0800 16 0801 16 : 0817 16 0818 16 : 0826 16 0827 16 0880 16 0881 16 : 0897 16 0e98 16 : 08a6 16 08a7 16 0900 16 0901 16 : 0917 16 0918 16 : 0926 16 0927 16 0980 16 0981 16 : 0997 16 0998 16 : 09a6 16 09a7 16 0a00 16 0a01 16 : 0a17 16 0a18 16 : 0a26 16 0a27 16 color code 2 specification 0828 16 0829 16 : 083f 16 0868 16 : 0876 16 0877 16 08a8 16 08a9 16 : 08bf 16 08e8 16 : 08f6 16 08f7 16 0928 16 0929 16 : 093f 16 0968 16 : 0976 16 0977 16 09a8 16 09a9 16 : 09bf 16 09e8 16 : 09f6 16 09f7 16 0a28 16 0a29 16 : 0a3f 16 0a68 16 : 0a76 16 0a77 16 display position (from left) 1st character 2nd character : 24th character 25th character : 39th character 40th character 1st character 2nd character : 24th character 25th character : 39th character 40th character 1st character 2nd character : 24th character 25th character : 39th character 40th character 1st character 2nd character : 24th character 25th character : 39th character 40th character 1st character 2nd character : 24th character 25th character : 39th character 40th character block block 1 block 2 block 3 block 4 block 5 table 14. contents of osd ram 2 2 2 2 2 ram for osd (addresses 0800 16 to 0fff 16 ) the ram for osd is allocated at addresses 0800 16 to 0fff 16 , and is divided into a display character code specification part, color code 1 specification part, and color code 2 specification part for each block. table 14 shows the contents of the ram for osd. for example, to display 1 character position (the left edge) in block 1, write the character code in address 0800 16 , write the color code 1 at 0840 16 , and write the color code 2 at 0828 16 . the structure of the ram for osd is shown in figure 68. note: for the osd mode block with dot size of 1.5t c 5 1/2h and 1.5t c 5 1h, the 3nth (n = 1 to 13) character is skipped as compared with ordinary block ] . accordingly, maximum 26 char- acters are only displayed in 1 block. the ram data for the 3nth character does not effect the display. any character data can be stored here (refer to figure 67). ] blocks with dot size of 1t c 5 1/2h and 1t c 5 1h, or blocks on the layer 1 color code 1 specification 0840 16 0841 16 : 0857 16 0858 16 : 0866 16 0867 16 08c0 16 08c1 16 : 08d7 16 08d8 16 : 08e6 16 08e7 16 0940 16 0941 16 : 0957 16 0958 16 : 0966 16 0967 16 09c0 16 09c1 16 : 09d7 16 08d8 16 : 09e6 16 09e7 16 0a40 16 0a41 16 : 0a57 16 0a58 16 : 0a66 16 0a67 16
mitsubishi microcomputers m37271mf-xxxsp m37271ef-xxxsp, m37271efsp single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller 60 color code 2 specification 0aa8 16 0aa9 16 : 0abf 16 0ae8 16 : 0af6 16 0af7 16 0b28 16 0b29 16 : 0b3f 16 0b68 16 : 0b76 16 0b77 16 0ba8 16 0ba9 16 : 0bbf 16 0be8 16 : 0bf6 16 0bf7 16 0c28 16 0c29 16 : 0c3f 16 0c68 16 : 0c76 16 0c77 16 0ca8 16 0ca9 16 : 0cbf 16 0ce8 16 : 0cf6 16 0cf7 16 0d28 16 0d29 16 : 0d3f 16 0d68 16 : 0d76 16 0d77 16 display position (from left) 1st character 2nd character : 24th character 25th character : 39th character 40th character 1st character 2nd character : 24th character 25th character : 39th character 40th character 1st character 2nd character : 24th character 25th character : 39th character 40th character 1st character 2nd character : 24th character 25th character : 39th character 40th character 1st character 2nd character : 24th character 25th character : 39th character 40th character 1st character 2nd character : 24th character 25th character : 39th character 40th character block block 6 block 7 block 8 block 9 block 10 block 11 table 14. contents of osd ram (continued) color code 1 specification 0ac0 16 0ac1 16 : 0ad7 16 0ad8 16 : 0ae6 16 0ae7 16 0b40 16 0b41 16 : 0b57 16 0b58 16 : 0b66 16 0b67 16 0bc0 16 0bc1 16 : 0bd7 16 0bd8 16 : 0be6 16 0be7 16 0c40 16 0c41 16 : 0c57 16 0c58 16 : 0c66 16 0c67 16 0cc0 16 0cc1 16 : 0cd7 16 0cd8 16 : 0ce6 16 0ce7 16 0d40 16 0d41 16 : 0d57 16 0d58 16 : 0d66 16 0d67 16 character code specification 0a80 16 0a81 16 : 0a97 16 0a98 16 : 0aa6 16 0aa7 16 0b00 16 0b01 16 : 0b17 16 0b18 16 : 0b26 16 0b27 16 0b80 16 0b81 16 : 0b97 16 0b98 16 : 0ba6 16 0ba7 16 0c00 16 0c01 16 : 0c17 16 0c18 16 : 0c26 16 0c27 16 0c80 16 0c81 16 : 0c97 16 0c98 16 : 0ca6 16 0ca7 16 0d00 16 0d01 16 : 0d17 16 0d18 16 : 0d26 16 0d27 16
mitsubishi microcomputers m37271mf-xxxsp m37271ef-xxxsp, m37271efsp single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller 61 display position (from left) 1st character 2nd character : 24th character 25th character : 39th character 40th character 1st character 2nd character : 24th character 25th character : 39th character 40th character 1st character 2nd character : 24th character 25th character : 39th character 40th character 1st character 2nd character : 24th character 25th character : 39th character 40th character 1st character 2nd character : 24th character 25th character : 39th character 40th character block block 12 block 13 block 14 block 15 block 16 table 14. contents of osd ram (continued) color code 1 specification 0dc0 16 0dc1 16 : 0dd7 16 0dd8 16 : 0de6 16 0de7 16 0e40 16 0e41 16 : 0e57 16 0e58 16 : 0e66 16 0e67 16 0ec0 16 0ec1 16 : 0ed7 16 0ed8 16 : 0ee6 16 0ee7 16 0f40 16 0f41 16 : 0f57 16 0f58 16 : 0f66 16 0f67 16 0fc0 16 0fc1 16 : 0fd7 16 0fd8 16 : 0fe6 16 0fe7 16 color code 2 specification 0da8 16 0da9 16 : 0dbf 16 0de8 16 : 0df6 16 0df7 16 0e28 16 0e29 16 : 0e3f 16 0e68 16 : 0e76 16 0e77 16 0ea8 16 0ea9 16 : 0ebf 16 0ee8 16 : 0ef6 16 0ef7 16 0f28 16 0f29 16 : 0f3f 16 0f68 16 : 0f76 16 0f77 16 0fa8 16 0fa9 16 : 0fbf 16 0fe8 16 : 0ff6 16 0ff7 16 character code specification 0d80 16 0d81 16 : 0d97 16 0d98 16 : 0da6 16 0da7 16 0e00 16 0e01 16 : 0e17 16 0e18 16 : 0e26 16 0e27 16 0e80 16 0e81 16 : 0e98 16 0e99 16 : 0ea6 16 0ea7 16 0f00 16 0f01 16 : 0f17 16 0f18 16 : 0f26 16 0f27 16 0f80 16 0f81 16 : 0f97 16 0f98 16 : 0fa6 16 0fa7 16 fig. 67. ram data for 3nth character 1 1 2 2 3 4 4 5 5 7 6 8 7 10 8 11 9 13 10 14 11 16 12 17 13 19 14 20 15 22 16 23 17 25 18 26 19 28 20 29 21 31 22 32 23 34 24 35 25 37 26 38 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 1 2 3 4 5 6 7 8 9 10111213141516171819202122232425262728293031323334353637383940 display sequence ram address order display sequence ram address order 1.5tc size block 1tc size block
mitsubishi microcomputers m37271mf-xxxsp m37271ef-xxxsp, m37271efsp single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller 62 note: do not read from and write to addresses in osd ram shown in table 15. table 15. list of access disable addresses 0878 16 08f8 16 0978 16 09f8 16 0a78 16 0af8 16 0b78 16 0bf8 16 0c78 16 0cf8 16 0d78 16 0df8 16 0e78 16 0ef8 16 0f78 16 0ff8 16 0879 16 08f9 16 0979 16 09f9 16 0a79 16 0af9 16 0b79 16 0bf9 16 0c79 16 0cf9 16 0d79 16 0df9 16 0e79 16 0ef9 16 0f79 16 0ff9 16 087a 16 08fa 16 097a 16 09fa 16 0a7a 16 0afa 16 0b7a 16 0bfa 16 0c7a 16 0cfa 16 0d7a 16 0dfa 16 0e7a 16 0efa 16 0f7a 16 0ffa 16
mitsubishi microcomputers m37271mf-xxxsp m37271ef-xxxsp, m37271efsp single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller 63 b0 rf6 rf5 rf4 rf3 rf2 rf1 rf0 rc17 rc16 rc15 rc14 rc13 rc12 rc11 rc10 rc23 rc22 rc21 rc20 rf7 b3 b0 b7 b0 b7 blocks 1 to16 character code color code 1 color code 2 fig. 68. structure of osd ram bit rf0 rf1 rf2 rf3 rf4 rf5 rf6 rf7 rc10 rc11 rc12 rc13 rc14 rc15 rc16 rc17 rc20 rc21 rc22 rc23 bit name character code (low-order 8 bits) character code (high-order 1 bit) control of character color r control of character color g control of character color b out1 control flash control underline control italic control control of background color r control of background color g control of background color b not used function specification of character code in osd rom 0: color signal output off 1: color signal output on 0: character output 1: background output 0: flash off 1: flash on 0: underline off 1: underline on 0: italic off 1: italic on 0: color signal output off 1: color signal output on bit name character code (low-order 8 bits) character code (high-order 1 bit) control of character color r control of character color g control of character color b out1 control control of character color i1 not used control of background color r control of background color g control of background color b control of background color i1 function specification of character code in osd rom 0: color signal output off 1: color signal output on 0: character output 1: background output 0: color signal output off 1: color signal output on 0: color signal output off 1: color signal output on bit name character code (low-order 8 bits) character code (high-order 1 bit) character color code 0 (cc0) character color code 1 (cc1) character color code 2 (cc2) out1 control extra code 0 (ex0) extra code 1 (ex1) extra code 2 (ex2) background color code 0 (bcc0) background color code 1 (bcc1) background color code 2 (bcc2) extra code 3 (ex3) function specification of character code in osd rom specification of character color 0: character output 1: background output specification of extra code in osd rom specification of background color specification of extra code in osd rom cc mode osd mode exosd mode notes 1: read value of bits 4 to 7 of the color code 2 is undefined. 2: for not used bits, the write value is read. 3: the decode value of the extra code is ex4.
mitsubishi microcomputers m37271mf-xxxsp m37271ef-xxxsp, m37271efsp single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller 64 i2 0 0 0 0 1 0 0 0 i2 0 0 0 0 1 0 0 0 b 0 0 0 0 0 1 1 1 i1 0 0 0 1 0 1 0 0 g 0 0 1 1 1 1 1 1 r 0 1 0 1 1 1 0 1 table 16. correspondence table of color code 1 and color signal output in exosd mode table 17. correspondence table of color code 2 and color signal output in exosd mode (7) character color the color for each character is displayed by the color code 1. the kinds and specification method of character color are different de- pending on each mode. ? cc mode .................. 7 kinds specified by bits 1 (r), 2 (g), and 3 (b) of the color code 1 ? osd mode ............... 15 kinds specified by bits 1 (r), 2 (g), 3 (b), and 5 (i1) of the color code 1 ? exosd mode .......... 7 kinds specified by bits 1 (cc0), 2 (cc1), and 3 (cc2) of the color code 1 the correspondence table of the color code 1 and color signal out- put in the exosd mode is shown in table 16. (8) character background color the character background color can be displayed in the character display area. the character background color for each character is specified by the color code 2. the kinds and specification method of character background color are different depending on each mode. ? cc mode .................. 7 kinds specified by bits 0 (r), 1 (g), and 2 (b) of the color code 2 ? osd mode ............... 15 kinds specified by bits 0 (r), 1 (g), 2 (b), and 3 (i1) of the color code 2 ? exosd mode .......... 7 kinds specified by bits 0 (bcc0), 1 (bcc1), and 2 (bcc2) of the color code 2 the correspondence table of the color code 2 and color signal output in the exosd mode is shown in table 17. note : the character background color is displayed in the following part : (character display area)C(character font)C(border)C(extra font). accordingly, the character background color does not mix with these color signal. bit 3 cc2 0 0 0 0 1 1 1 1 bit 2 cc1 0 0 1 1 0 0 1 1 bit 1 cc0 0 1 0 1 0 1 0 1 r 0 1 0 1 1 1 0 1 g 0 0 1 1 1 1 1 1 b 0 0 0 0 0 1 1 1 i1 0 0 0 1 0 1 0 0 color code 1 bit 2 bcc2 0 0 0 0 1 1 1 1 bit 1 bcc1 0 0 1 1 0 0 1 1 bit 0 bcc0 0 1 0 1 0 1 0 1 color code 2 color signal output color signal output
mitsubishi microcomputers m37271mf-xxxsp m37271ef-xxxsp, m37271efsp single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller 65 (9) out1, out2 signals the out1, out2 signals are used to control the luminance of the video signal. the output waveform of the out1, out2 signals is controlled by bit 4 of the color code 1 (refer to figure 68), bits 2 and fig. 69. setting value for controlling out1, out2 and corresponding output waveform 7 of the block control register (refer to figure 53). the setting values for controlling out1, out2 and the corresponding output waveform is shown in figure 69. 0 1 0 1 0 1 0 1 0 1 0 1 0 1 out1 out2 out1 out2 out1 out2 out1 out2 out1 out2 out1 out2 out1 out2 out1 out2 block control register out2 output control bit (b7) border output control bit (b2) output waveform out1 control (b4 of color code 1)
mitsubishi microcomputers m37271mf-xxxsp m37271ef-xxxsp, m37271efsp single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller 66 4 4 4 4 4 extra font there are 32 kinds of the extra fonts configured with 16 5 26 dots in osd rom. 16 kinds of these fonts can be displayed by ored with the character font by a character unit (refer to figure 50). for the others, only the extra font is displayed (refer to figure 50). in only the exosd mode, the extra font is controlled the following : bits 7 to 5 of the color code 1, bit 3 of the color code 2, and decode value (ex4) of the character code. when the character code = 00 16 to 13f 16 , ex4 is 0, when the character code = 140 16 , ex4 is 1. since there is no font with the character code = 140 16 , a blank is dis- played. the extra font color for each screen is specified by the extra color register. when the character font overlaps with the extra font, the color of the area becomes the ored color of both fonts. note : when using the extra font, set bits 7 and 6 of the osd control register to 0 (refer to figure 52). fig. 70. structure of extra font color register (10) attribute the attributes (flash, underline, italic) are controlled to the character font. the attributes for each character are specified by the color codes 1 and 2 (refer to figure 68). the attributes to be controlled are differ- ent depending on each mode. cc mode ..................... flash, underline, italic osd mode .................. border (all bordered, shadow bordered can be selected) exosd mode ............. border (all bordered, shadow bordered can be selected) , extra font (32 kinds) 1 1 1 1 1 under line the underline is output at the 23th and 24th dots in vertical direction only in the cc mode. the underline is controlled by bit 6 of the color code 1. the color of underline is the same color as that of the char- acter font. 2 2 2 2 2 flash the parts of the character font, the underline, and the character back- ground are flashed only in the cc mode. the color signals (r, g, b, out1) of the character font and the underline are controlled by bit 5 of the color code 1. all of the color signals for the character font flash. however, the color signal for the character background can be con- trolled by bit 3 of the osd control register (refer to figure 52). the flash cycle bases on the v sync count. v sync cycle 5 48 ; 768 ms (at flash on) v sync cycle 5 16 ; 256 ms (at flash off) 3 3 3 3 3 italic the italic is made by slanting the font stored in osd rom only in the cc mode. the italic is controlled by bit 7 of the color code 1. the display example of the italic and underline is shown in figure 70. in this case, 16 26 dots are used and r is displayed. notes 1: when setting both the italic and the flash, the italic charac- ter flashes. 2: when the pre-divide ratio = 1, the italic character with slant of 1 dot 5 5 steps is displayed (refer to figure 71 (c)). when the pre-divide ratio = 2, the italic character with slant of 1/2 dot 5 10 steps is displayed (refer to figure 71 (d)). 3: the boundary of character color is displayed in italic. how- ever, the boundary of character background color is not af- fected by the italic (refer to figure 72). 4: the adjacent character (one side or both side) to an italic character is displayed in italic even when the character is not specified to display in italic (refer to figure 72). 5: when displaying the italic character in the block with the pre-divide ratio = 1, set the osd clock frequency to 11 mhz to 14 mhz. 7 extra font color register (ec : address 0218 16 ) extra font color r control bit 0 : no output 1 : output extra font color g control bit 0 : no output 1 : output extra font color b control bit 0 : no output 1 : output extra font color i1 control bit 0 : no output 1 : output extra font color i2 control bit 0 : no output 1 : output 0
mitsubishi microcomputers m37271mf-xxxsp m37271ef-xxxsp, m37271efsp single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller 67 fig. 72. example of italic display fig. 71. example of attribute display (in cc mode) 0 0 10 0 1 0 1 color code 1 bit 6 bit 7 color code 1 bit 6 bit 7 color code 1 bit 6 bit 7 color code 1 bit 6 bit 7 (a) ordinary (b) underline (c) italic (pre-divide ratio = 1) (d) italic (pre-divide ratio = 2 ) 10 0 1 1 0 1 italic on one side italic on both sides bit 7 of color code 1 note : the wavy-lined is the boundary of character color
mitsubishi microcomputers m37271mf-xxxsp m37271ef-xxxsp, m37271efsp single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller 68 5 5 5 5 5 border the border is output in the osd mode and the exosd mode. the all bordered (bordering around of character font) and the shadow bor- dered (bordering right and bottom sides of character font) are se- lected (refer to figure 73) by bit 2 of the osd control register (refer to figure 52). the border on/off is controlled by bit 2 of the block control register (refer to figure 53). the out1 signal is used for border output. the border color for each screen is specified by the border color register. the horizontal size (x) of border is 1t c (osd clock cycle divided in the pre-divide circuit) regardless of the character font dot size. the vertical size (y) different depending on the screen scan mode and the vertical dot size of character font. notes 1 : there is no border for the extra font. 2 : the border dot area is the shaded area as shown in figure 75. in the exosd mode, top and bottom of character font display area is not bordered. 3 : when the border dot overlaps on the next character font, the character font has priority (refer to figure 76 a). when the border dot overlaps on the next character back ground, the border has priority (refer to figure 76 b). 4 : the border is not displayed at right side of the most right dot in the display area of the 40th character (the character located at the most right of the block). fig. 73. example of border display fig. 74. horizontal and vertical size of border all bordered shadow bordered y x 1/2h 1h, 2h, 3h 1/2h, 1h, 2h, 3h 1/2h 1h 1h vertical dot size of character font border dot size scan mode horizontal size (x) vertical size (y) normal scan mode bi-scan mode 1t c (osd clock cycle divided in pre-divide circuit)
mitsubishi microcomputers m37271mf-xxxsp m37271ef-xxxsp, m37271efsp single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller 69 fig. 75. border area fig. 76. border priority fig. 77. structure of border color register 70 border color register (fc : address 021b 16 ) border color r control b 0 : no output 1 : output border color g control bit 0 : no output 1 : output border color b control bit 0 : no output 1 : output border color i1 control bit 0 : no output 1 : output border color i2 control bit 0 : no output 1 : output character boundary b character boundary a character boundary b 16 dots 16 dots 20 dots osd mode exosd mode 1 dot width of border 1 dot width of border 1 dot width of border 1 dot width of border character font area 20 dots
mitsubishi microcomputers m37271mf-xxxsp m37271ef-xxxsp, m37271efsp single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller 70 (11) multiline display the m37271mf-xxxsp can ordinarily display 16 lines on the crt screen by displaying 16 blocks at different vertical positions. in addi- tion, it can display up to 16 lines by using osd interrupts. an osd interrupt request occurs at the point at which display of each block has been completed. in other words, when a scanning line reaches the point of the display position (specified by the vertical position registers) of a certain block, the character display of that block starts, and an interrupt occurs at the point at which the scan- ning line exceeds the block. the mode in which an osd interrupt occurs is different depending on the setting of the raster color regis- ter (refer to figure 84). when bit 7 of the raster color register is 0 an osd interrupt occurs at the end of block display in the osd and the exosd mode. when bit 7 of the raster color register is 1 an osd interrupt occurs at the end of block display in the cc mode. notes 1: an osd interrupt does not occur at the end of display when the block is not displayed. in other words, if a block is set to off display by the display control bit of the block control reg- ister (addresses 00d0 16 to 00df 16 ), an osd interrupt re- quest does not occur (refer to figure 78 (a)). 2: when another block display appeares while one block is displayed, an osd interrupt request occurs only once at the end of the another block display (refer to figure 78 (b)). 3: on the screen setting window, an osd interrupt occurs even at the end of the cc mode block (off display) out of window (refer to figure 78 (c)). fig. 78. note on occurence of osd interrupt (b) (c) block 1 (on display) block 2 (on display) block 3 (on display) block 4 (on display) block 1 (on display) block 2 (on display) block 3 (off display) block 4 (off display) osd interrupt request osd interrupt request osd interrupt request osd interrupt request osd interrupt request osd interrupt request no osd interrupt request block 1 block 2 osd interrupt request osd interrupt request osd interrupt request osd interrupt request block 1 block 2 block 3 on display (osd interrupt request occurs at the end of block display) off display (osd interrupt request does not occur at the end of block display) in cc mode window no osd interrupt request no osd interrupt request (a)
mitsubishi microcomputers m37271mf-xxxsp m37271ef-xxxsp, m37271efsp single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller 71 bit 4 of osd control register bit 7 of block control register bit 4 of color code 1 out1 output signal out2 output signal notes 1 : blank is disabled on the left side of the 1st character and on the right side of the 40th character of each block. 2 : when using this function, set 009 16 to the 40th character. (12) automatic solid space function this function generates automatically the solid space (out1 or out2 blank output) of the character area in the cc mode. the solid space is output in the following area : the character area except character code 009 16 the character area on the left and right sides of the character area except character code 009 16 this function is turned on and off by bit 4 of the osd control register (refer to figure 52). 0 01 character character font part display area off table 18. setting for automatic solid space 0 1 01 character font part off character display area 0 01 solid space off 1 1 01 character font part solid space fig. 79. display screen example of automatic solid space 009 005 009 009 009 006 006 16 16 16 16 16 16 16 006 009 16 16 ? ? ? ? 009 16 009 16 when setting the character code ?05 16 ?as the character a, ?06 16 ?as the character b. (display memory) character to be displayed (display screen) 1st character 2nd character ( note 1 ) no blank output 39th character 40th character ( note 2 )( note 1 )
mitsubishi microcomputers m37271mf-xxxsp m37271ef-xxxsp, m37271efsp single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller 72 (13) scan mode m37271mf-xxxsp has the bi-scan mode for corresponding to h sync of double speed frequency. in the bi-scan mode, the vertical start display position and the vertical size is two times as compared with the normal scan mode. the scan mode is selected by bit 1 of the osd control register (refer to figure 52). (14) window function this function sets the top and bottom boundary of display limit on a screen. the window function is valid only in the cc mode. the top boundary is set by the window h registers 1 and 2. the bottom bound- ary is set by the window l registers 1 and 2. this function is turned on and off by bit 5 of the osd control register (refer to figure 52). the structure of the window h registers 1 and 2 is shown in figure 81, the structure of the window l registers 1 and 2 is shown in figure 82. notes 1: set values except 00 16 and 01 16 to the window h regis- ter 1 when the window h register 2 is 00 16 . 2: set the register value fit for the following condition : (wh1 + wh2) < (wl1 + wl2) bit 1 of osd control register vertical display start position vertical dot size table 19. setting for scan mode normal scan 0 value of vertical position register 5 1h 1t c 5 1/2h 1t c 5 1h 2t c 5 2h 3t c 5 3h bi-scan 1 value of vertical position register 5 2h 1t c 5 1h 1t c 5 2h 2t c 5 4h 3t c 5 6h scan mode parameter fig. 80. example of window function exosd mode window fgh i j cc mode kl mno cc mode pqrst cc mode osd mode bottom boundary of window top boundary of window screen abcde uvwxy
mitsubishi microcomputers m37271mf-xxxsp m37271ef-xxxsp, m37271efsp single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller 73 fig. 82. structure of window l registers fig. 81. structure of window h registers window l register 1 (wl1 : address 021d ) control bits of window bottom boundary (note) bottom boundary position (low-order 8bits) t h 5 (setting value of low-order 2bits of wl2 5 16 +setting value of high-order 4bits of wl1 5 16 +setting value of low-order 4bits of wl1 5 16 ) 2 0 1 window l register 2 (wl2 : address 021f ) control bits of window bottom boundary (note) bottom boundary position (high-order 2bits) t h 5 (setting value of low-order 2bits of wl2 5 16 +setting value of high-order 4bits of wl1 5 16 +setting value of low-order 4bits of wl1 5 16 ) 2 0 1 note : set values fit for the following condition : (wh1+wh2) < (wl1+wl2). 16 16 window h register 1 (wh1 : address 021c ) control bits of window top boundary (note) top boundary position (low-order 8bits) t h 5 (setting value of low-order 2bits of wh2 5 16 +setting value of high-order 4bits of wh1 5 16 +setting value of low-order 4bits of wh1 5 16 ) 2 0 1 window h register 2 (wh2 : address 021e ) control bits of window top boundary (note) top boundary position (high-order 2bits) t h 5 (setting value of low-order 2bits of wh2 5 16 +setting value of high-order 4bits of wh1 5 16 +setting value of low-order 4bits of wh1 5 16 ) 2 0 1 note : set values except 00 16 and 01 16 to the wh1 when the wh2 is 00 16. 16 16 7 0 7 0 7 0 7 0
mitsubishi microcomputers m37271mf-xxxsp m37271ef-xxxsp, m37271efsp single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller 74 (15) osd output pin control the osd output pins r, g, b, and out1 can also function as ports p5 2 , p5 3 , p5 4 and p5 5 . set the corresponding bit of the osd port control register (address 00cb 16 ) to 0 to specify these pins as osd output pins, or set it to 1 to specify it as a general-purpose port p5 pins. the out2, i1, and i2 can also function as port p1 0 , p1 5 , p1 6 . set the corresponding bit of the port p1 direction register (address 00c3 16 ) to 1 (output mode). after that, switch between the osd output function and the port function by the osd port control regis- ter. set the corresponding bit to 1 to specify the pin as osd output pin, or set it to 0 to specify as port p1 pin. the input polarity of the h sync , v sync and output polarity of signals r, g, b, i1, i2, out1 and out2 can be specified with the i/o polarity control register (address 0217 16 ) . set a bit to 0 to specify positive polarity; set it to 1 to specify negative polarity (refer to figure 64). the structure of the osd port control register is shown in figure 83. fig. 83. structure of osd port control register 70 0 osd port control register (pf : address 00cb 16 ) port p1 5 output signal selection bit 0 : port p1 5 output 1 : i1 signal output port p1 6 output signal selection bit 0 : port p1 6 output 1 : i2 signal output port p5 2 output signal selection bit 0 : r signal output 1 : port p5 2 output port p5 3 output signal selection bit 0 : g signal output 1 : port p5 3 output port p5 4 output signal selection bit 0 : b signal output 1 : port p5 4 output port p5 5 output signal selection bit 0 : out1 signal output 1 : port p5 5 output port p1 0 output signal selection bit 0 : port p1 0 output 1 : out2 signal output fix this bit to ?.
mitsubishi microcomputers m37271mf-xxxsp m37271ef-xxxsp, m37271efsp single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller 75 (16) raster coloring function an entire screen (raster) can be colored by setting the bits 6 to 0 of the raster color register. since each of the r, g, b, i1, i2, out1, and out2 pins can be switched to raster coloring output, 7 raster colors can be obtained. if the out1 pin has been set to raster coloring output, a raster color- ing signal is always output during 1 horizontal scanning period. this setting is necessary for erasing a background tv image. if the r, g, b, i1, and i2 pins have been set to output, a raster color- ing signal is output in the part except a no-raster colored character (in figure 85, a character 1) during 1 horizontal scanning period. this ensures that character colors are not mixed with the raster color. the structure of the raster color register is shown in figure 84, the example of raster coloring is shown in figure 85. fig. 84. structure of raster color register fig. 85. example of raster coloring h sync aaaaaaaaaaa a aaaaaaaaa a a aaaaaaaaa a a aaaaaaaaa a a aaaaaaaaa a a aaaaaaaaa a aaaaaaaaaaa a' a out1 r g b a : character color ?ed?(r) : border color ?reen?(g) : background color ?agenta?(r and b) : raster color ?lue?(r and out1) signals across a-a' 70 raster color register (rc : address 0218 16 ) raster color r control bit 0 : no output 1 : output raster color g control bit 0 : no output 1 : output raster color b control bit 0 : no output 1 : output raster color i1 control bit 0 : no output 1 : output raster color i2 control bit 0 : no output 1 : output raster color out1 control bit 0 : no output 1 : output raster color out2 control bit 0 : no output 1 : output osd interrupt source selection bit 0 : interrupt occurs at end of osd or exosd block display 1 : interrupt occurs at end of cc mode block display
mitsubishi microcomputers m37271mf-xxxsp m37271ef-xxxsp, m37271efsp single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller 76 interrupt interval determination function the m37271mf-xxxsp incorporates an interrupt interval determi- nation circuit. this interrupt interval determination circuit has an 8-bit binary up counter as shown in figure 86. using this counter, it deter- mines an interval or a pulse width on the int1 or int2 (refer to fig- ure 88). the following describes how the interrupt interval is determined. 1. the determination mode is selected by using bit 5 of the interrupt interval determination control register (address 0212 16 ). when this bit is set to 0, the interrupt interval determination mode is se- lected; when the bit is set to 1, the pulse width determination mode is selected. 2. the interrupt input to be determined (int1 input or int2 input) is selected by using bit 2 in the interrupt interval determination con- trol register (address 0212 16 ). when this bit is cleared to 0, the int1 input is selected ; when the bit is set to 1, the int2 input is selected. 3. when the int1 input is to be determined, the polarity is selected by using bit 3 of the interrupt interval determination control register ; when the int2 input is to be determined, the polarity is selected by using bit 4 of the interrupt interval determination control register. when the relevant bit is cleared to 0, determination is made of the interval of a positive polarity (rising transition) ; when the bit is set to 1, determination is made of the interval of a negative po- larity (falling transition). 4. the reference clock is selected by using bit 1 of the interrupt inter- val determination control register. when the bit is cleared to 0, a 32 m s clock is selected ; when the bit is set to 1, a 16 m s clock is selected (based on an oscillation frequency of 8mhz in either case). 5. simultaneously when the input pulse of the specified polarity (rising or falling transition) occurs on the int1 pin (or int2 pin), the 8-bit binary up counter starts counting up with the selected reference clock (32 m s or 16 m s). 6. simultaneously with the next input pulse, the value of the 8-bit binary up counter is loaded into the interrupt interval determina- tion register (address 0211 16 ) and the counter is immediately re- set (00 16 ). the reference clock is input in succession even after the counter is reset, and the counter restarts counting up from 00 16 . 7. when count value fe 16 is reached, the 8-bit binary up counter stops counting. then, simultaneously when the next reference clock is input, the counter sets value ff 16 to the interrupt inter- val determination register. the reference clock is generated by setting bit 0 of the pwm mode register 1 to 0.
mitsubishi microcomputers m37271mf-xxxsp m37271ef-xxxsp, m37271efsp single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller 77 fig. 88. setting value of interrpt interval determination control register and measuring interval fig. 86. block diagram of interrupt interval determination circuit fig. 87. structure of interrupt interval determination control register re 5 0 0 1 1 re i 0 1 0 1 int1 or int2 input count interval re i : bit i (i = 3, 4) of interrupt interval determination control register (address 0211 16 ) 8 data bus control circuit connected to black colored side at rest. selection gate : (address 0211 16 ) 32 m s re 1 16 m s 8-bit binary up counter (8) interrupt interval determination register(8) re 0 8 int1 (note) re 2 int2 (note) note: the pulse width of external interrupt int1 and int2 needs 5 or more machine cycles. re: input interval determination control register 0 7 interrupt interval determination control register (re : address 0212 16 ) interrupt interval determination circuit operation control bit 0 : stopped 1 : operating external interrupt input pin selection bit 0 : int1 input 1 : int2 input int1 pin input polarity switch bit 0 : positive polarity input 1 : negative polarity input int2 pin input polarity switch bit 0 : positive polarity input 1 : negative polarity input interrupt interval determination mode switch bit 0 : interrupt interval determination mode 1 : pulse width determination mode reference clock control selection bit (at f(x in ) = 8mhz) 0 : 32 m s 1 : 16 m s int3 pin input polarity switch bit 0 : positive polarity input 1 : negative polarity input a-d conversion int3 interrupt source selection bit 0 : int3 interrupt 1 : a-d conversion interrupt
mitsubishi microcomputers m37271mf-xxxsp m37271ef-xxxsp, m37271efsp single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller 78 reset circuit the m37271mf-xxxsp is reset according to the sequence shown in figure 90. it starts the program from the address formed by using the content of address ffff 16 as the high-order address and the content of the address fffe 16 as the low-order address, when the ______ reset pin is held at l level for 2 m s or more while the power source voltage is 5 v 10 % and the oscillation of a quartz-crystal oscillator or a ceramic resonator is stable and then returned to h level. the internal state of microcomputer at reset are shown in figures 3 to 7. an example of the reset circuit is shown in figure 89. the reset input voltage must be kept 0.9 v or less until the power source voltage surpasses 4.5 v. fig. 90. reset sequence fig. 89. example of reset circuit x in f reset internal reset sync address data 32768 count of x in clock cycle (note 3) reset address from the vector table ? ? 01, s 01, s-1 01, s-2 fffe ffff ad h , ad l ? ? ? ? ? ad l ad h notes 1 : f(x in ) and f( f ) are in the relation : f(x in ) = 2f ( f ). 2 : a question mark (?) indicates an undefined state that depends on the previous state. 3 : immediately after a reset, timer 3 and timer 4 are connected in hardware. at this time, ff 16 is set in timer 3 and 07 16 is set to timer 4. timer 3 counts down with f(x in )/16, and reset state is released by the timer 4 overflow signal. power source voltage 0 v reset input voltage 0 v 4.5 v 0.9 v poweron 32 36 33 vcc reset vss m37271mf-xxxsp 1 5 4 3 0.1 m f m51953al
mitsubishi microcomputers m37271mf-xxxsp m37271ef-xxxsp, m37271efsp single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller 79 fig. 91. i/o pin block diagram (1) ports p0 3 , p1 0 , p1 5 ?1 7 , p2, p3 0 , p3 1 data bus direction register port latch data bus direction register port latch data bus direction register port latch ports p0 0 ?0 2 , p0 4 ?0 7 ports p1 1 ?1 4 n-channel open-drain output ports p0 0 Cp0 2 , p0 4 Cp0 7 note : each port is also used as below : p0 0 Cp0 2 : pwm4Cpwm6 p0 4 Cp0 7 : pwm0Cpwm3 n-channel open-drain output port p1 1 -p1 4 note : each port is also used as below : p1 1 : scl1 p1 2 : scl2 p1 3 : sda1 p1 4 : sda2 cmos output ports p0 3 , p1 0 , p1 5 Cp1 7 , p2, p3 0 , p3 1 note : each port is also used as below : p1 0 : out2 p1 5 : i1 p1 6 : i2/int3 p1 7 : s in p2 4 Cp2 6 : ad3Cad1
mitsubishi microcomputers m37271mf-xxxsp m37271ef-xxxsp, m37271efsp single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller 80 n-channel open-drain output ports s out , s clk note : each pin is also used as below : s out : p4 5 s clk : p4 6 r, g, b, out1 note : each pin is also used as below : r : p5 2 b : p5 4 g : p5 3 out1 : p5 5 cmos output h sync , v sync schmidt input fig. 92. i/o pin block diagram (2) ports p4 0 Cp4 4 note : each port is also used as below : p4 0 : ad4 p4 1 : int2 p4 2 : tim2 p4 3 : tim3 p4 4 : int1 h sync , v sync s out , s clk r, g, b, out1 data bus direction register internal circuit data bus ports p4 0 ?4 4 internal circuit
mitsubishi microcomputers m37271mf-xxxsp m37271ef-xxxsp, m37271efsp single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller 81 clock generating circuit the m37271mf-xxxsp has 2 built-in oscillation circuits. an oscilla- tion circuit can be formed by connecting a resonator between x in and x out (x cin and x cout ). use the circuit constants in accordance with the resonator manufacturers recommended values. no exter- nal resistor is needed between x in and x out since a feed-back re- sistor exists on-chip. however, an external feed-back resistor is needed between x cin and x cout . when using x cin -x cout as sub- clock, clear bits 5 and 4 of the clock source control register to 0. to supply a clock signal externally, input it to the x in (x cin ) pin and make the x out (x cout ) pin open. when not using x cin clock, con- nect the x cin to v ss and make the x cout pin open. after reset has completed, the internal clock f is half the frequency of x in . immediately after poweron, both the x in and x cin clock start oscillating. to set the internal clock f to low-speed operation mode, set bit 7 of the cpu mode register (address 00fb 16 ) to 1. oscillation control (1) stop mode the built-in clock generating circuit is shown in figure 93. when the stp instruction is executed, the internal clock f stops at h level. at the same time, timers 3 and 4 are connected in hardware and ff 16 is set in the timer 3, 07 16 is set in the timer 4. select f(x in )/16 or f(x cin )/16 as the timer 3 count source (set both bit 0 of the timer mode register 2 and bit 6 at address 00c7 16 to 0 before the execu- tion of the stp instruction). and besides, set the timer 3 and timer 4 interrupt enable bits to disabled (0) before execution of the stp instruction. the oscillator restarts when external interrupt is accepted, however, the internal clock f keeps its h level until timer 4 over- flows. because this allows time for oscillation stabilizing when a ce- ramic resonator or a quartz-crystal oscillator is used. (2) wait mode when the wit instruction is executed, the internal clock f stops in the h level but the oscillator continues running. this wait state is released at reset or when an interrupt is accepted (note). since the oscillator does not stop, the next instruction can be executed at once. note: in the wait mode, the following interrupts are invalid. (1) v sync interrupt (2) osd interrupt (3) timers 1 and 2 interrupts using p4 2 /tim2 pin input as count source (4) timer 3 interrupt using p4 3 /tim3 pin input as count source (5) data slicer interrupt (6) multi-master i 2 c-bus interface interrupt (7) f(x in )/4096 interrupt (8) all timer interrupts using f(x in )/2 or f(x cin )/2 as count source (9) all timer interrupts using f(x in )/4096 or f(x cin )/4096 as count source (10) a-d conversion interrupt fig. 93. ceramic resonator circuit example fig. 94. external clock input circuit example (3) low-speed mode if the internal clock is generated from the sub-clock (x cin ), a low power consumption operation can be realized by stopping only the main clock x in . to stop the main clock, set bit 6 (cm 6 ) of the cpu mode register (00fb 16 ) to 1. when the main clock x in is restarted, the program must allow enough time to for oscillation to stabilize. note that in low-power-consumption mode the x cin -x cout drivability can be reduced, allowing even lower power consumption (60 m a with f (x cin ) = 32khz). to reduce the x cin -x cout drivability, clear bit 5 (cm 5 ) of the cpu mode register (00fb 16 ) to 0. at reset, this bit is set to 1 and strong drivability is selected to help the oscillation to start. when an stp instruction is executed, set this bit to 1 by soft- ware before executing. x cin x in c cin m37271mf-xxxsp x cout r f r d c cout x out c in c out x cin m37271mf-xxxsp external oscillation circuit or external pulse x cout x in x out open open external oscillation circuit vcc vss vcc vss
mitsubishi microcomputers m37271mf-xxxsp m37271ef-xxxsp, m37271efsp single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller 82 fig. 95. clock generating circuit block diagram x cin x cout osc1 oscillating mode selection bits (notes 1, 4) internal system clock selection bit (notes 1, 3) internal system clock selection bit (notes 1, 3) main clock (x in ? out ) stop bit (notes 1, 3) r s q stp instruction wit instruction r s q reset interrupt disable flag i interrupt request r s q reset stp instruction timing f (internal clock) timer 3 count source selection bit (notes 1, 2) ? timer 3 count stop bit (notes 1, 2) timer 4 count stop bit (notes 1, 2) timer 3 timer 4 1/2 1/8 x out x in ? ? ? notes 1 : the value at reset is ?. 2 : refer to the structure of timer mode register 2. 3 : refer to the structure of cpu mode register (next page). 4 : refer to the structure of clock source control register.
mitsubishi microcomputers m37271mf-xxxsp m37271ef-xxxsp, m37271efsp single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller 83 fig. 96. state transitions of system clock reset the example assumes that 8 mhz is being applied to the x in pin and 32 khz to the x cin pin. the f indicates the internal clock. wit instruction cm 7 : internal system clock selection bit 0 : x in -x out selected (high-speed mode) 1 : x cin -x cout selected (low-speed mode) cpu mode register (address : 00fb 16 ) cm 6 : main clock (x in ? out ) stop bit 0 : oscillating 1 : stopped 8mhz oscillating 32khz oscillating f is stopped (?? timer operating 8mhz oscillating 32khz oscillating f( f ) = 4mhz 8mhz stopped 32khz stopped f is stopped (?? 8mhz oscillating 32khz oscillating f is stopped (?? timer operating (note 3) 8mhz oscillating 32khz oscillating f( f ) = 16khz 8mhz stopped 32khz stopped f is stopped (?? 8mhz stopped 32khz stopped f = stopped (?? 8mhz stopped 32khz oscillating f( f ) = 16khz 8mhz stopped 32khz oscillating f is stopped (?? timer operating (note 3) interrupt stp instruction interrupt (note 1) wit instruction interrupt wit instruction interrupt stp instruction interrupt (note 2) stp instruction interrupt (note 2) cm 7 = 1 cm 7 = 0 cm 6 = 1 cm 6 = 0 external int, timer interrupt, or si/o interrupt external int notes 1: when the stp state is ended, a delay of approximately 8ms is automatically generated by timer 3 and timer 4. 2: the delay after the stp state ends is approximately 2s. 3: when the internal clock f divided by 8 is used as the timer count source, the frequency of the count source is 2khz. the program must allow time for 8mhz oscillation to stabilize high-speed operation start mode
mitsubishi microcomputers m37271mf-xxxsp m37271ef-xxxsp, m37271efsp single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller 84 display oscillation circuit the osd oscillation circuit has a built-in clock oscillation circuits, so that a clock for osd can be obtained simply by connecting an lc, a ceramic resonator, or a quartz-crystal oscillator across the pins osc1 and osc2. which of the sub-clock or the osd oscillation circuit is selected by setting bits 5 and 4 of the clock source control register (address 0216 16 ). addressing mode the memory access is reinforced with 17 kinds of addressing modes. refer to the series 740
mitsubishi microcomputers m37271mf-xxxsp m37271ef-xxxsp, m37271efsp single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller 85 prom programming method the built-in prom of the one time prom version (blank) and built- in eprom version can be read or programmed with a general-pur- pose prom programmer using a special programming adapter. product m37271efsp name of programming adapter pca7400 the prom of the one time prom version (blank) is not tested or screened in the assembly process and following processes. to en- sure proper operation after programming, the procedure shown in figure 99 is recommended to verify programming. fig. 99. programming and testing of one time prom version programming with prom programmer screening (caution) (150? for 40 hours) verification with prom programmer functional check in target device caution : the screening temperature is far higher than the storage temperature. never expose to 150? exceeding 100 hours. data required for mask orders the following are necessary when ordering a mask rom produc- tion: (1) mask rom order confirmation form (2) mark specification form (3) data to be written to rom, in eprom form ( 32-pin dip type 27c101, three identical copies)
mitsubishi microcomputers m37271mf-xxxsp m37271ef-xxxsp, m37271efsp single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller 86 7.9 29 11.0 26.5 15.262 1.5 limits power source voltage v cc , av cc input voltage cnv ss input voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 , p3 1 , p4 0 Cp4 6 , p6 4 , osc1, ______ x in , h sync , v sync , reset, cv in output voltage p0 3 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 , p3 1 , r, g, b, out1, s out , s clk , x out , osc2 output voltage p0 0 Cp0 2 , p0 4 Cp0 7 circuit current r, g, b, out1, out2, p0 3 , p1 5 Cp1 7 , p2 0 Cp2 7 , p3 0 , p3 1 circuit current r, g, b, out1, out2, p0 3 , p1 5 Cp1 7 , p2 0 Cp2 7 , s out , s clk circuit current p1 1 Cp1 4 circuit current p0 0 Cp0 2 , p0 4 Cp0 7 circuit current p3 0 , p3 1 power dissipation operating temperature storage temperature symbol v cc , av cc v i v i v o absolute maximum ratings conditions all voltages are based on v ss . output transistors are cut off. parameter C0.3 to 13 0 to 1 (note 1) 0 to 2 (note 2) 0 to 6 (note 2) 0 to 1 (note 2) 0 to 10 (note 3) 550 C10 to 70 C40 to 125 v ma ma ma ma ma mw c c min. 4.5 2.0 0 0.8v cc 0.7v cc 0 0 0 typ. 5.0 0 max. 5.5 5.5 0 v cc v cc 0.4 v cc 0.3 v cc 0.2 v cc 1 2 input frequency tim2, tim3, int1, int2, int3 input frequency s clk input frequency scl1, scl2 input frequency horizontal sync. signal of video signal input amplitude video signal cv in v v v v v v v v ma ma recommended operating conditions (t a = C10 c to 70 c, v cc = 5 v 10 %, unless otherwise noted) power source voltage (note 4), during cpu, osd, data slicer operation ram hold voltage (when clock is stopped) power source voltage h input voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 , p3 1, ______ p4 0 Cp4 6 , p6 4 , h sync , v sync , reset, x in , osc1 h input voltage p1 1 Cp1 4 (when using i 2 c-bus) l input voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 , p3 1, p4 0 Cp4 6 , p6 3 , p6 4 l input voltage scl1, scl2, sda1, sda2, (when using i 2 c-bus) l input voltage (note 6) p4 1 Cp4 4 , p4 6 , p1 6 , p1 7 , h sync , v sync , ______ reset, x in , osc1 h average output current (note 1) r, g, b, out1, out2, p0 3 , p1 5 Cp1 7 , p2 0 Cp2 7 , p3 0 , p3 1 l average output current (note 2) r, g, b, out1, out2, p0 3 , p1 5 Cp1 7 , p2 0 Cp2 7 , s out , s clk l average output current (note 2) p1 1 Cp1 4 l average output current (note 2) p0 0 Cp0 2 , p0 4 Cp0 7 l average output current (note 3) p3 0 , p3 1 oscillation frequency (for cpu operation) (note 5) x in oscillation frequency (for sub-clock operation) x cin v cc , av cc v cc , av cc v ss v ih1 v ih2 v il1 v il2 v il3 i oh i ol1 symbol parameter unit f hs1 f hs2 f hs3 f hs4 v i khz mhz khz khz v mhz ma ma ma mhz khz 6 1 10 8.1 35 27.0 27.5 100 1 400 16.206 2.5 8.0 32 27.0 15.734 2.0 i ol2 i ol3 i ol4 f cpu f clk v o i oh i ol1 i ol2 i ol3 i ol4 p d t opr t stg oscillation frequency (for osd) osc1 f osd lc oscillating mode ceramic oscillating mode t a = 25 c unit v v v v ratings C0.3 to 6 C0.3 to 6 C0.3 to v cc + 0.3 C0.3 to v cc + 0.3
mitsubishi microcomputers m37271mf-xxxsp m37271ef-xxxsp, m37271efsp single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller 87 ma m a ma m a v v max. 30 45 200 4 100 10 0.4 limits power source current h output voltage r, g, b, out1, out2, p0 3 , p1 5 Cp1 7 , p2 0 Cp2 7 , p3 0 , p3 1 l output voltage r, g, b, out1, out2, s out , s clk , p0 0 Cp0 7 , p1 5 Cp1 7 , p2 0 Cp2 7 l output voltage p3 0 , p3 1 l output voltage p1 1 Cp1 4 hysteresis ______ reset hysteresis (note 6) h sync , v sync , p4 1 Cp4 4 , p4 6 , p1 1 Cp1 4 , p1 7 h input leak current ______ reset, p0 3 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 , p3 1 , p4 0 Cp4 6 , p6 3 , p6 4 , h sync , v sync l input leak current ______ reset, p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 , p3 1 , p4 0 Cp4 6 , p6 3 , p6 4 , h sync , v sync h input leak current p0 0 Cp0 2 , p0 4 Cp0 7 i 2 c-busbus switch connection resistor (between scl1 and scl2, sda1 and sda2) min. 2.4 electric characteristics (v cc = 5 v 10 %, v ss = 0 v, f(x in ) = 8 mhz, t a = C10 c to 70 c, unless otherwise noted) i cc v oh v ol typ. 15 30 60 2 25 1 symbol parameter test conditions unit wait mode stop mode system operation v cc = 5.5 v, f(x in ) = 0, f(x cin ) = 32khz, osd off, data slicer off, low-power dissipation mode set (cm 5 = 0, cm 6 = 1) v cc = 5.5 v, f(x in ) = 8 mhz v cc = 5.5 v, f(x in ) = 0, f(x cin ) = 32khz, low-power dissipation mode set (cm 5 = 0, cm 6 = 1) v cc = 5.5 v, f(x in ) = 0, f(x cin ) = 0 v cc = 4.5 v i oh = C0.5 ma v cc = 4.5 v i ol = 0.5 ma crt off data slicer off crt on data slicer on v cc = 5.5 v, f(x in ) = 8 mhz 0.5 0.5 3.0 0.4 0.6 0.7 1.3 5 5 10 130 v t+ Cv tC i izh i izl i izh r bs v m a m a m a w v cc = 4.5 v i ol = 10.0 ma v cc = 4.5 v i ol = 3 ma i ol = 6 ma v cc = 5.0 v v cc = 5.0 v v cc = 5.5 v v i = 5.5 v v cc = 5.5 v v i = 0 v v cc = 5.5 v v i = 12 v v cc = 4.5 v notes 1: the total current that flows out of the ic must be 20 or less. 2: the total input current to ic (i ol1 + i ol2 + i ol3 ) must be 20 ma or less. 3: the total average input current for ports p3 0 , p3 1 to ic must be 10 ma or less. 4: connect 0.1 m f or more capacitor externally across the power source pins v cc Cv ss and av cc Cv ss so as to reduce power source noise. also connect 0.1 m f or more capacitor externally across the pins v cc Ccnv ss . 5: use a quartz-crystal oscillator or a ceramic resonator for the cpu oscillation circuit. when using the data slicer, use 8 mhz. 6: p1 6 , p4 1 Cp4 4 have the hysteresis when these pins are used as interrupt input pins or timer input pins. p1 1 Cp1 4 have the hysteresis when these pins are used as multi-master i 2 c-bus interface ports. p1 7 and p4 6 have the hysteresis when these pins are used as serial i/o pins. 7: when using the sub-clock, set f clk < f cpu /3.
mitsubishi microcomputers m37271mf-xxxsp m37271ef-xxxsp, m37271efsp single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller 88 a-d converter characteristics (v cc = 5 v 10 %, v ss = 0 v, f(x in ) = 8 mhz, t a = C10 c to 70 c, unless otherwise noted) resolution non-linearity error differential non-linearity error zero transition error full-scale transition error conversion time reference voltage ladder resistor analog input current max. 8 2 0.9 2 4 12.5 v cc v ref bits lsb lsb lsb lsb m s v k w v min. 0 0 0 0 12.25 0 limits typ. unit test conditions parameter symbol v ot v fst t conv v ref r ladder v ia v cc = 5.12v i ol (sum) = 0ma v cc = 5.12v 25 multi-master i 2 c-bus bus line characteristics bus free time hold time for start condition l period of scl clock rising time of both scl and sda signals data hold time h period of scl clock falling time of both scl and sda signals data set-up time set-up time for repeated start condition set-up time for stop condition t buf t hd:sta t low t r t hd:dat t high t f t su:dat t su:sta t su:sto max. 1000 300 min. 1.3 0.6 1.3 20+0.1c b 0 0.6 20+0.1c b 100 0.6 0.6 max. 300 0.9 300 m s m s m s ns m s m s ns ns m s m s unit standard clock mode high-speed clock mode parameter symbol note: c b = total capacitance of 1 bus line fig. 100. definition diagram of timing on multi-master i 2 c-bus min. 4.7 4.0 4.7 0 4.0 250 4.7 4.0 sda scl p t buf s t hd : sta t low t r t hd : dat t high t f t su : dat t su : sta sr p t su : sto t hd : sta
mitsubishi microcomputers m37271mf-xxxsp m37271ef-xxxsp, m37271efsp single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller 89 package outline
mitsubishi microcomputers m37271mf-xxxsp m37271ef-xxxsp, m37271efsp single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller 90 gzz?h10?4b < 5za0 > 740 family mask rom confirmation form single-chip microcomputer m37271mf-xxxsp mitsubishi electric mask rom number date : supervisor signature receipt section head signature * customer company name date issued date : tel ( ) note : please fill in all items marked * . submitted by supervisor issuance signature * 1. confirmation specify the name of the product being ordered and the type of eproms submitted. three eproms are required for each pattern. if at least two of the three sets of eproms submitted contain identical data, we will produce masks based on this data. we shall assume the responsibility for errors only if the mask rom data on the products we produce differs from this data. thus, extreme care must be taken to verify the data in the submitted eproms. checksum code for entire eprom (hexadecimal notation) 27c101 eprom address 00000 16 product name ascii code : ?37271mf 0000f 16 0ffff 16 set ?f 16 ?in the shaded area. write the ascii codes that indicates the product name of ?37271mf to addresses 0000 (1) (2) eprom type (indicate the type used) 01000 16 osd rom 1e43f 16 * 2. mark specification mark specification must be submitted using the correct form for the type package being ordered fill out the appropriate mark specification form (52p4b for m37271mf-xxxsp) and attach to the mask rom confirmation form. do you set ?f 16 ?in the shaded area ? do you write the ascii codes that indicates the product name of ?37271mf to addresses 0000 16 to 000f 16 ? eprom data check item (refer the eprom data and check ? ?in the appropriate box) ? yes ? yes l l 10800 16 data rom 60k bytes 16 to 000f 16 .
mitsubishi microcomputers m37271mf-xxxsp m37271ef-xxxsp, m37271efsp single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller 91 gzz?h10?4b < 5za0 > 740 family mask rom confirmation form single-chip microcomputer m37271mf-xxxsp mitsubishi electric ? = 16 4d 16 ? = 33 16 ? = 3 7 16 ? = 3 2 16 ? = 37 16 ? = 3 1 16 ? = 4d 16 ? = 46 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 address = 16 2d 16 ff 16 ff 16 ff 16 ff 16 ff 16 ff 16 ff 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 address addresses 00000 16 to 0000f 16 store the product name, and addresses 10800 16 to 1e43f 16 store the character pattern. if the name of the product contained in the eproms does not match the name on the mask rom confirmation form, the rom processing is disabled. write the data correctly. inputting the name of the product with the ascii code ascii codes ?37271mf-?are listed on the right. the addresses and data are in hexadecimal notation. 1. inputting the character rom input the character rom data to character rom. for the character rom data, see the next page and on. 2. writing the product name and character rom data onto eproms
mitsubishi microcomputers m37271mf-xxxsp m37271ef-xxxsp, m37271efsp single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller 92 gzzCsh10C44b < 5za0 > 740 family mask rom confirmation form single-chip microcomputer m37271mf-xxxsp mitsubishi electric font data must be stored in the proper osd rom address according to the following table. (3/4) (2)osd rom address of extra font data (1)osd rom address of character font data line number = 02 16 to 15 16 character code = 00 16 to 13f 16 font bit = 0 : left font 1 : right font osd rom address bit line number / character code / font bit ad16 ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 10 font bit line number character code osd rom address bit line number / extra code / font bit ad16 ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 11 font bit line number extra code 0000 example) the font data 60 (shaded area ) of the character code aa 16 is stored in address 1 0 0 1 0 1 0 0 1 0 1 0 1 0 1 0 0 2 =12954 16 . 02 16 03 16 04 16 05 16 06 16 07 16 08 16 09 16 0a 16 0b 16 0c 16 0d 16 0e 16 0f 16 10 16 11 16 12 16 13 16 14 16 15 16 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 left font right font line number (1) character code aa 16 line number 19 16 (2) extra code 0a 16 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 left font right font 00 16 01 16 02 16 03 16 04 16 05 16 06 16 07 16 08 16 09 16 0a 16 0b 16 0c 16 0d 16 00 16 00 16 10 16 11 16 12 16 13 16 14 16 15 16 16 16 17 16 18 16 line number = 00 16 to 19 16 extra code = 00 16 to 1f 16 font bit = 0 : left font 1 : right font example) the font data 03 (shaded area ) of the extra code 0a 16 is stored in address 1 1 0 0 1 0 1 0 0 0 0 0 1 0 1 0 1 2 =19415 16 .
mitsubishi microcomputers m37271mf-xxxsp m37271ef-xxxsp, m37271efsp single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller 93 gzz?h10?4b < 5za0 > 740 family mask rom confirmation form single-chip microcomputer m37271mf-xxxsp mitsubishi electric 10a80 16 to 10bff 16 10e80 16 to 10fff 16 11280 16 to 113ff 16 11680 16 to 117ff 16 11a80 16 to 11bff 16 11e80 16 to 11fff 16 12280 16 to 123ff 16 12680 16 to 127ff 16 12a80 16 to 12bff 16 12e80 16 to 12fff 16 13280 16 to 133ff 16 13680 16 to 137ff 16 13a80 16 to 13bff 16 13e80 16 to 13fff 16 14280 16 to 143ff 16 14680 16 to 147ff 16 14a80 16 to 14bff 16 14e80 16 to 14fff 16 15280 16 to 153ff 16 15680 16 to 17fff 16 18040 16 to 183ff 16 18440 16 to 187ff 16 18840 16 to 18bff 16 18c40 16 to 18fff 16 19040 16 to 193ff 16 19440 16 to 197ff 16 19840 16 to 19bff 16 19c40 16 to 19fff 16 1a040 16 to 1a3ff 16 1a440 16 to 1a7ff 16 1a840 16 to 1abff 16 1ac40 16 to 1afff 16 1b040 16 to 1b3ff 16 1b440 16 to 1b7ff 16 1b840 16 to 1bbff 16 1bc40 16 to 1bfff 16 1c040 16 to 1c3ff 16 1c440 16 to 1c7ff 16 1c840 16 to 1cbff 16 1cc40 16 to 1cfff 16 1d040 16 to 1d3ff 16 1d440 16 to 1d7ff 16 1d840 16 to 1dbff 16 1dc40 16 to 1dfff 16 1e040 16 to 1e3ff 16 the following osd rom addresses must be set ?f.?there are no font data in these addresses.
mitsubishi microcomputers m37271mf-xxxsp m37271ef-xxxsp, m37271efsp single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller 94 52p4b (52-pin shrink dip) mark specification form
mitsubishi microcomputers m37271mf-xxxsp m37271ef-xxxsp, m37271efsp single-chip 8-bit cmos microcomputer with closed caption decoder and on-screen display controller 95 shrink dip mark specification form for one time prom version microcomputers
? 1997 mitsubishi electric corp. new publication, effective nov. 1997. specifications subject to change without notice. notes regarding these materials these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product b est suited to the customer?s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-party?s rights, origina ting in the use of any product data, diagrams, charts or circuit application examples contained in these materials. all information contained in these materials, including product data, diagrams and charts, represent information on products a t the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that customers co ntact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used und er circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use of a pro duct contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these m aterials. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a licen se from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is pro hibited. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further detai ls on these materials or the products contained therein. keep safety first in your circuit designs! mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making y our circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
rev. rev. no. date 1.0 first edition 9708 2.0 information about copyright note, revision number, release date added (last page). 971130 (1/1) revision description revision description list m37271ef-xxxsp, m37271efsp data sheet m37271mf-xxxsp
